Attacks on the HF Physical Layer of Contactless and RFID Systems

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MATRICES DE DETECTEURS BOLOMETRIQUES POUR L'IMAGERIE DANS LES BANDES MILLIMETRIQUES (FAISABILITE, PERFORMANCES ET REALISATION D'UN DEMONSTRATEUR)

GRENOBLE1-BU Sciences (384212103) / SudocSudocFranceF

Participation au dépistage du cancer colorectal par le test Hémoccult II® (étude sur la population cible dans l'Hérault)

MONTPELLIER-BU Médecine UPM (341722108) / SudocMONTPELLIER-BU Médecine (341722104) / SudocPARIS-BIUM (751062103) / SudocSudocFranceF

Memory Authenticated Encryption Eengine for a RISC-V processor

International audienceIn this paper, we present the Memory Authenticated Encryption Engine (MAEE) hardware countermeasureto ensure the confidentiality and authenticity of data in RAM and the associated interconnect bus. Using the Subterranean 2.0 authenticated encryption algorithm, data used by a processor is secured at the output of cache memory, and stored in memory as chunks, containing encrypted data and metadata for authenticity verification. The MAEE provides protection against attacks targeting the memory and its bus, such as Rowhammer, fault injections or side-channel attacks. We are also evaluating the performance of this countermeasure, by associating it with the RISC-V CVA6 application core.Dans ce papier, nous présentons la contremesure hardware Memory Authenticated Encryption Engine (MAEE) permettant de garantir la confidentialité et l'authenticité des données dans la mémoire RAM et dans le bus d'interconnexion associé. En utilisant l'algorithme de chiffrement authentifié Subterranean 2.0, les données utilisées par un processeur sont sécurisées en sortie de mémoire cache, et stockées en mémoire sous forme de bloc, contenant les données chiffrées et des métadonnées pour la vérification de l'authenticité. Le MAEE permet de se prémunir des attaques ciblant la mémoire et son bus comme Rowhammer, les injections de fautes ou les attaques Side-Channel. Nous évaluons également les performances de cette contremesure, en l'associant au coeur d'application RISC-V CVA6

SecDec: Secure Decode Stage thanks to masking of instructions with the generated signals

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SecDec: Secure Decode Stage thanks to masking of instructions with the generated signals

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Insertion of random delay with context-aware dummy instructions generator in a RISC-V processor

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Confidaent: Control flow protection with instruction and data authenticated encryption

International audienceComputing devices became part of our daily world. But being physically accessible they are exposed to a very large panel of physical attacks, which are most of the time underestimated. These systems must include protections against these attacks in order to keep user data secret and safe. In this work, we argue that addressing the security requirements of embedded processors with independent countermeasures is not the most efficient strategy and may introduce security flaws in the process. Instead, we suggest a more monolithic approach to security design. Following this idea, we propose a new efficient and flexible memory encryption & authentication mechanism called CONFIDAENT, that can protect code and data in embedded processors. On the top of this primitive, we build a strong Control Flow Integrity (CFI) countermeasure. We describe a RISC-V instruction set extension to support these mechanisms and the compiler support needed in the LLVM framework. This new countermeasure is developed on a modified RISCY RISC-V core and its performances are evaluated on a FPGA target. We conclude that a truly high-security can be achieved, with an overhead factor of ×2.66 up to ×3.73 on execution time of benchmarks programs

Lightweight Software Encryption for Embedded Processors

International audienceOver the last 30 years, a number of secure processor architectures have been proposed to protect software integrity and confidentiality during its distribution and execution. In such architectures, encryption (together with integrity checking) is used extensively, on any data leaving a defined secure boundary. In this paper, we show how encryption can be achieved at the instruction level using a stream cipher. Thus encryption is more lightweight and efficient, and is maintained deeper in the memory hierarchy than the natural off-chip boundary considered in most research works. It requires the control flow graph to be used and modified as part of the off-line encryption process, but thanks to the LLVM framework, it can be integrated easily in a compiler pipeline, and be completely transparent to the programmer. We also describe hardware modifications needed to support this encryption method, the latter were added to a 32 bit MIPS soft core. The synthesis performed on a Altera Cyclone V FPGA shows that encryption requires 26% of extra logic, while slowingdown execution time by an average of 48% in the best setting