Overview of the SiLC R&D Activities

The R&D Collaboration SiLC (Silicon tracking for Linear Colliders) is based on generic R&D aiming to develop the next generation of large Silicon tracking systems for the Linear collider experiments; it serves all three ILC detector concepts. There is a strong involvement in ILD, a natural collaboration with SiD and recent 4th concept interest to use Silicon tracking technology as well. Here is a very brief summary of the latest results on sensors, Front End Electronics, Mechanics and Integration issues, test bench and test beam results and where to go from there.Comment: 3 pages, 3 figures, LCWS08 Worksho

Level-1 pixel based tracking trigger algorithm for LHC upgrade

The Pixel Detector is the innermost detector of the tracking system of the Compact Muon Solenoid (CMS) experiment at CERN Large Hadron Collider (LHC). It precisely determines the interaction point (primary vertex) of the events and the possible secondary vertexes due to heavy flavours ($b$ and $c$ quarks); it is part of the overall tracking system that allows reconstructing the tracks of the charged particles in the events and combined with the magnetic field to measure their impulsion. The pixel detector allows measuring the tracks in the region closest to the interaction point. The Level-1 (real-time) pixel based tracking trigger is a novel trigger system that is currently being studied for the LHC upgrade. An important goal is developing real-time track reconstruction algorithms able to cope with very high rates and high flux of data in a very harsh environment. The pixel detector has an especially crucial role in precisely identifying the primary vertex of the rare physics events from the large pile-up (PU) of events. The goal of adding the pixel information already at the real-time level of the selection is to help reducing the total level-1 trigger rate while keeping an high selection capability. This is quite an innovative and challenging objective for the experiments upgrade for the High Luminosity LHC (HL-LHC). The special case here addressed is the CMS experiment. This document describes exercises focusing on the development of a fast pixel track reconstruction where the pixel track matches with a Level-1 electron object using a ROOT-based simulation framework.Comment: Submitted to JINST; 12 pages, 10 figures, Contribution to the JINST proceedings for the INFIERI2014 School in Paris, France, July 14-25, 201

Large Silicon Tracking Systems for ILC: Role, Design and Main issues

The roles, the designs, the main issues and the current status of the R&D on large Silicon Tracking Systems for the ILC are discussed in this paper. The R&D work presented here is performed within the SiLC (Silicon tracking for the Linear Collider) R&D Collaboration

Large Area Silicon Tracking: New Perspectives

The successful running of the large area Silicon trackers of ATLAS and CMS at LHC, and the ongoing R&D for the upgrade of these tracking systems, in various stages, over this decade, are a full proof of this technology and of its still impressive potential. The Linear Collider project is waiting for the possible discovery of a light Higgs at LHC maybe by end of 2012. These facts opened a new phase for the R&D on Silicon tracking for the Linear Collider, with enhanced synergy with LHC, Astrophysics and other HEP experiments, thus leading to new perspectives and alternatives.Comment: LCWS2011 Proceedings, 10 page

A new 130nm F.E readout chip for microstrip detectors

In the context of the Silicon tracking for a Linear Collider (SiLC) R&D collaboration, a highly compact mixed-signal chip has been designed in 130nm CMOS technology intended to read Silicon strip detectors for the experiments at the future International Linear Collider. The chip includes eighty eight channels of a full analog signal processing chain and analog to digital conversion with the corresponding digital controls and readout channels. The chip is 5x10mm2 where the analog implementation represents 4/5 of the total Silicon area.Comment: 3 pages, 4 figures, LCWS08 worksho

Silicon Data Acquisition and Front-End Electronics

A highly integrated Front-End readout and Data Acquisition scheme for Silicon trackers is presented. In this context, a 16-channel readout chip for Silicon strips detector has been designed in 180nm CMOS technology, having in view a highly multiplexed and sparsified readout global strategy. First results are presented

Front-End and Readout Electronics for Silicon Trackers at the ILC

A highly integrated readout scheme for Silicon trackers making use of Deep Sub-Micron CMOS electronics is presented. In this context,a 16-channel readout chip for Silicon strips detector has been designed in 180nm CMOS technology, each channel comprising a low noise amplifier, a pulse shaper, a sample and hold and a comparator. First results are presented

Pixel data real time processing as a next step for HL-LHC upgrades and beyond

The experiments at LHC are implementing novel and challenging detector upgrades for the High Luminosity LHC, among which the tracking systems. This paper reports on performance studies, illustrated by an electron trigger, using a simplified pixel tracker. To achieve a real-time trigger (e.g. processing HL-LHC collision events at 40 MHz), simple algorithms are developed for reconstructing pixel-based tracks and track isolation, utilizing look-up tables based on pixel detector information. Significant gains in electron trigger performance are seen when pixel detector information is included. In particular, a rate reduction up to a factor of 20 is obtained with a signal selection efficiency of more than 95\% over the whole $\eta$ coverage of this detector. Furthermore, it reconstructs p-p collision points in the beam axis (z) direction, with a high precision of 20 $\mu$m resolution in the very central region ($|\eta| < 0.8$), and, up to 380 $\mu$m in the forward region (2.7 $< |\eta| <$ 3.0). This study as well as the results can easily be adapted to the muon case and to the different tracking systems at LHC and other machines beyond the HL-LHC. The feasibility of such a real-time processing of the pixel information is mainly constrained by the Level-1 trigger latency of the experiment. How this might be overcome by the Front-End ASIC design, new processors and embedded Artificial Intelligence algorithms is briefly tackled as well.Comment: To be submitted to JHE

Extraction of the x-dependence of the non-perturbative QCD b-quark fragmentation distribution component

Using recent measurements of the b-quark fragmentation distribution obtained in $e^+e^- \to b \bar{b}$ events registered at the Z pole, the non-perturbative QCD component of the distribution has been extracted independently of any hadronic physics modelling. This distribution depends only on the way the perturbative QCD component has been defined. When the perturbative QCD component is taken from a parton shower Monte-Carlo, the non-perturbative QCD component is rather similar with those obtained from the Lund or Bowler models. When the perturbative QCD component is the result of an analytic NLL computation, the non-perturbative QCD component has to be extended in a non-physical region and thus cannot be described by any hadronic modelling. In the two examples used to characterize these two situations, which are studied at present, it happens that the extracted non-perturbative QCD distribution has the same shape, being simply translated to higher-x values in the second approach, illustrating the ability of the analytic perturbative QCD approach to account for softer gluon radiation than with a parton shower generator.Comment: 13 page

Silicon Avalanche Pixel Sensor for High Precision Tracking

The development of an innovative position sensitive pixelated sensor to detect and measure with high precision the coordinates of the ionizing particles is proposed. The silicon avalanche pixel sensors (APiX) is based on the vertical integration of avalanche pixels connected in pairs and operated in coincidence in fully digital mode and with the processing electronics embedded on the chip. The APiX sensor addresses the need to minimize the material budget and related multiple scattering effects in tracking systems requiring a high spatial resolution in the presence of a large occupancy. The expected operation of the new sensor features: low noise, low power consumption and suitable radiation tolerance. The APiX device provides on-chip digital information on the position of the coordinate of the impinging charged particle and can be seen as the building block of a modular system of pixelated arrays, implementing a sparsified readout. The technological challenges are the 3D integration of the device under CMOS processes and integration of processing electronics.Comment: 13th Topical Seminar on Innovative Particle and Radiation Detectors IPRD1