Low-power low-voltage chopped transconductance amplifier for noise and offset reduction

This paper describes the principle and design of a CMOS low-power, low-voltage, chopped transconductance amplifier, for noise and offset reduction in mixed analogue digital applications. The operation is based on chopping and dynamic element matching, to reduce noise and offset, without excessive increase of the charge injection residual offset. Experimental results show residual offsets of less than 150µV at 100kHz chopping frequency, a signal to noise ratio of 95dB, in audio band, for 100KHz chopping and a THD of -89dB. The power consumption is 594µW

A Ka band, static, MCML frequency divider, in standard 90nm-CMOS LP for 60 GHz applications

This paper presents a broadband, static, 2:1 frequency divider in a bulk 90 nm CMOS LP (low-power) technology with maximum operating frequency of 35.5 GHz. The divider exhibits an enhanced input sensitivity, below 0 dBm, over a broad input range of 31 GHz and consumes 24 mA from a 1.2 V supply. The phase noise of the divider is -124.6 dBc/Hz at 1 MHz offset from the carrier

A 40 GHz, broadband, highly linear amplifier, employing T-coil bandwith extension technique

This paper presents a broadband, highly linear amplifier suitable for multi-standard mm-wave applications such as car radar, LMDS and satellite return channel. It can also be utilized as an efficient wideband output buffer, for measurements of mm-wave circuit components. It exhibits a 3-dB bandwidth of 40 GHz with a pass-band gain of 6 dB. The presented amplifier is highly linear with an IP3 of +18 dBm. It has been implemented in a bulk 90 nm CMOS LP (low power) technology and consumes 3.3 mW from a 1.2 V supply

A 40 GHz, broadband, highly linear amplifier, employing T-coil bandwith extension technique

This paper presents a broadband, highly linear amplifier suitable for multi-standard mm-wave applications such as car radar, LMDS and satellite return channel. It can also be utilized as an efficient wideband output buffer, for measurements of mm-wave circuit components. It exhibits a 3-dB bandwidth of 40 GHz with a pass-band gain of 6 dB. The presented amplifier is highly linear with an IP3 of +18 dBm. It has been implemented in a bulk 90 nm CMOS LP (low power) technology and consumes 3.3 mW from a 1.2 V supply

Receiver Front-End Circuits for Future Generations of Wireless Communications

In this paper, new receiver concepts and CMOS circuits for future wireless communications standards are introduced. Tradeoffs between technology, performance and circuit choices of the RF front-end circuits are discussed. In particular, power consumption, noise figure and linearity trade-offs in low-noise amplifiers, mixers and oscillators are considered. The concepts derived are applied to a few classes of wireless communications standards that are broadband in nature at RF and/or require a broadband IF. Multi-mode, multi-band operation and adaptability as key requirements for future generation receivers are highlighted throughout the paper