This paper describes the principle and design of a CMOS low-power, low-voltage, chopped transconductance amplifier, for noise and offset reduction in mixed analogue digital applications. The operation is based on chopping and dynamic element matching, to reduce noise and offset, without excessive increase of the charge injection residual offset. Experimental results show residual offsets of less than 150µV at 100kHz chopping frequency, a signal to noise ratio of 95dB, in audio band, for 100KHz chopping and a THD of -89dB. The power consumption is 594µW

Nauta, B.

Sanduleanu, M.A.T.

Wallinga, H.

English

Nauta, Bram

Wallinga, Hans

University of Twente Research Information

LOW-POWER LOW-VOLTAGE CHOPPEDTRANSCONDUCTANCE AMPLIFIER FORNOISE AND OFFSET REDUCTIONM.A.T. Sanduleanu1, B. Nauta2 and H.Wallinga11University of Twente, Department of Electrical Engineering  P.O.Box 217, 7500 AE Enschede, The NetherlandsE_mail: m.a.t.sanduleanu@el.utwente.nl                     2Philips Research Laboratories, Prof. Holstlaan 4, 5656 AAEindhoven, The NetherlandsABSTRACTThis paper describes the principle and design of a CMOS low-power, low-voltage, chopped transconductance amplifier, for noise and offset reductionin mixed analogue digital applications. The operation is based on choppingand dynamic element matching, to reduce noise and offset, withoutexcessive increase of the charge injection residual offset. Experimentalresults show residual offsets of less than 150µV at 100kHz choppingfrequency, a signal to noise ratio of 95dB, in audio band, for 100KHzchopping and a THD of -89dB. The power consumption is 594µW.1.  INTRODUCTIONThe CMOS technology for mixed signal applications becomes less and less compatible withanalog requirements due to the process tuning towards digital needs. As a consequence foranalog functions built in digital CMOS the signal swing reduces with power supply and sodoes the dynamic range. Besides, 1/f noise properties are worsened for surface PMOST’s incomparison to buried transistors, with an order of magnitude, and this under the conditions ofa heavy crosstalk via the substrate from digital functions. At 3.3V and a 0.5µm CMOStechnology, the substrate bounce can reach 300mV in amplitude with spectral contributions inGHz range, further reducing the voltage swing [1], [4]. In conventional chopper stabilizedopamps for 1/f noise and offset reduction, differential amplifiers are being used andbandwidth is limited to few tens of kHz [2]. Switching at the differential output will introducemost of the switching noise and residual offset. This paper presents a choppedtransconductance amplifier which circumvents the above mentioned drawbacks. The choppingfrequency can reach MHz range without excessive increase in offset.2.  CIRCUIT PRINCIPLEFig.1 shows the circuit diagram. The input chopper M10, M11, M13 and M15 transposes thedifferential input signal applied to the terminals IN+ and IN- to the alternate output nodes.Fig.1: Circuit diagramAs a result, the signal is modulated at odd harmonics of the chopper frequency. The second chopperM19, M20, M21 and M22 demodulates the signal and modulates 1/f noise and offset at oddharmonics. A cascoded mirror M24, M25, M12 and M14  performs a broadband differential tosingle ended conversion. The need for large bandwidth implies small transistor lengths for M12 andM14 and therefore extra offset and 1/f noise. For this reason a third chopper is being introduced inthe signal path: M27, M28, M29 and M30. The transistors M12 and M14 are dynamically matched[3] without consequences on signal. The unswitched cascode transistors provide furtherimprovement in switching noise and residual offset by low pass filtering some of the HF noisecomponents generated from chopping and keeping low voltage swings at their sources. In order tominimize substrate interferences, only PMOS transistors and NMOS switches with smalldimensions are being used in the signal path [4]. The oxide capacitance of M34 decouples the BIASline to VSS. Substrate interferences present in the sources of cascode transistors M23 and M26 willbe also present at their gates such that gate source voltages of the same transistors can be consideredconstant for HF substrate noise [4]. For the same reason, the current sources M6 and M7 have theirgates decoupled to VSS via a large capacitance.3.  NOISE AND OFFSETNeglecting the noise introduced by cascode transistors and switches, the power spectral density ofthe white and 1/f noise referred to the input is:( )( )( )( )( )Sv fkTgggggkW L fkkW LW LggW LW Lggw f mmmmmFP FNFPmmmm+ = ∗ + + + ∗ + +1/ 262122 2 22 26 66222 212 121222832 1 2 1( ) (1)where kFN and kFP are process dependent constants. Large transconductances of the differential inputpair give low white noise. 1/f noise can be minimized by increasing the area of the input pair andincreasing the transconductance of the input transistors in comparison to the transconductances ofM6 and M12. If ∆VT denotes the threshold mismatch, ∆β/β the relative gain factor mismatch, VGTthe effective gate voltage (VGS-VT), n the slope factor and UT the thermal voltage, the offset voltagereferred to the input can be computed from: ( ) ( ) ( ) ( )σ σ σ ββ σ σββσ σββV V n Un UVV n Un UVV n UOS T TTGTT TTGTT T= + + + + +∆∆∆∆∆∆22 2 2 222 2 2122 122 2 2 12122 2 262 62 2 2 772164328 (2)The dominant terms in the offset voltage are due to the threshold mismatch of the input pair and thethreshold mismatch of M12 and M14. Large phase margins can be obtained when M12 and M14have small lengths. This increases their contribution to the offset and noise. Dynamic elementmatching is being used to reduce this effect. Fig.2 shows the simulated static dynamic range of theOTA and the static offset as a function of the bias current JBIAS. The OTA has been configured asa follower with 10MHz gain bandwidth product (GBW). By scaling down the current according toW scaling [1] and keeping the same power supply voltage and GBW, a factor 10 reduction in powergives a 10dB reduction in DR. This can be seen also from the DR*GBW product of the OTA. If Pdenotes the total power, ∆ the saturation limits at the output node, n the slope factor and NEF thenoise excess factor DR*GBW is:DR GBWPn KT NEFVU VDDT DD∗ = −80122π∆         (3)By chopping, the offset of the amplifier is removed in the same way as 1/f noise. Charge injection inthe input modulator causes spikes at the input and this gives residual offset. The residual offset in afollower configuration and after low pass filtering can be computed from:Vos residual VinjjkT Tjk Tg Cj kTTom gskk odd,///= −+ +=−∞=∞∑ 41 2 1 22 230ππ π(4)Vinj represents the amplitude of the spikes at the input, T0 the time constant of the charge injected, Tis the chopping period and Cgs23 the gate-source capacitance of M23 and M26. By using Poissonsummation rule for series and considering gm2/2πCgs23 larger than Fchopp, we get:( )( ) ( )Vos residual Vinjg CT g CT g CT g CT TT TVinjT Fm gsm gsm gsm gschopp,// /tanh //tanh //=−−≅2 230 2 232 232 2300021 242422 (5)This shows an increase of the residual offset with chopping frequency and the energy of the spikes.4.   EXPERIMENTAL RESULTSThe chopped transconductance amplifier hasbeen realized in a 0.5 µm CMOS technology.For measurements purposes OTA has beenconfigured as a follower with a bias current of30 µA. Fig.3 shows the static offset and theresidual offset for 6 arbitrarily chosen circuitsamples after low pass filtering the output.Without chopping (Fchopp=0), static offsetsof  less than 680µV can occur. Chopping willreduce the offset for relatively low chopperfrequencies but increasing the choppingfrequency the residual offset will increase.This is in close agreement with eq. (5).  TheFig.2: DR(static) and offset(static)residual offset at 100KHz chopping frequency is less than 150µV. At low chopping frequencies, aminimum in residual offset occurs. Fig.4 shows the signal to noise plus distortion figure (SINAD)for 100KHz chopping and 1KHz input. The input signal at 0dB reaches 2.8Vpp where distortion ishigh and dominates SINAD. For low signal amplitudes the noise level is higher than the distortionlevel. The measured signal to noise ratio in audio band (0..20KHz) after chopping is -95dB andharmonic distortion (THD) is -89dB at -15dB signal level. Chopping increases signal to noise ratiowith about 6dB. The same performance can be achieved without chopping but increasing the powerconsumption 4 times (2.4mW) as estimated by eq.(3). Fig.5 shows the chip photo and Table1 aperformance summary of the circuit.   Fig.3: Static(Fchopp=0) and residual offset Fig.4: SINAD at Fchopp=93KHzFig.5: Chip photo5.   CONCLUSIONSOpen-loop gain >75dBGBW 10MHzOffset(static) <1.1mVOffset(chopped) <370µVChopping frequency Fchopp≤1MHzS/N|Fchopp=93KHz 95dBS/N|Fchopp=0 89dBHarmonic distortion -89dBSupply voltage 3.3V±10%Power consumption 594µWTechnology 0.5µm, 2PS,3AL, CMOSArea 0.0308mm2Table 1: Performance summaryA low-voltage, low-power, chopped transconductance amplifier for mixed analogue digitalapplications has been presented. Chopping and dynamic element matching allow low noise and lowresidual offsets up to 1MHz. The unswitched cascode transistors provide further improvement inresidual offset and switching noise by low pass filtering some of the HF components generated fromchopping. The sensitivity to substrate noise is taken into account in the design. Experimental resultsshow residual offsets of less than 150µV at 100KHz chopping frequency and a signal to noise ratioin audio band of 95dB at 93KHz chopping. The power consumption is 594µW at 3.3V supply.ACKNOWLEDGEMENTSThe authors acknowledge the help of M. Dijkstra from Philips Research during measurements.REFERENCES[1] B. Nauta,  “Analog CMOS low-power design considerations”, Low-Power Low-voltage      workshop at ESSCIRC’96, Neuchatel-Switzerland, September 1996.[2] K.C. Hsieh et al., “A low-noise chopper-stabilized differential switched-capacitor filtering      technique,” IEEE J. Solid-State Circuits, vol. SC-18, pp. 708-715, Dec. 1981.[3] R.J. van de Plassche et al., “A monolithic 14-bit D/A converter,” IEEE J. Solid-State Circuits,      vol. SC-14, pp.552-556, June 1979.[4] B. Nauta and G.Hoogzaad, “How to deal with substrate noise in analog CMOS circuits”,     European Conference on Circuit Theory and Design, Budapest, September 1997.

Low-power low-voltage chopped transconductance amplifier for noise and offset reduction

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A low-noise chopper-stabilized differential switched-capacitor filtering technique,”

A monolithic 14-bit D/A converter,”

Analog CMOS low-power design considerations”, Low-Power Low-voltage workshop at ESSCIRC’96,

How to deal with substrate noise in analog CMOS

http://purl.utwente.nl/publications/15974

Low-power low-voltage chopped transconductance amplifier for noise and offset reduction

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