A 32kb 10T subthreshold SRAM array with bit-interleaving and differential read scheme in 90nm CMOS

We demonstrate a 10T subthreshold SRAM with an efficient bit-interleaving structure for soft-error tolerance and a differential read scheme for improved stability. The 32kb (256128) SRAM array is fabricated in 90nm CMOS and operates at 31.25kHz at 0.18V With more aggressive wordline boosting, the V DD can be reduced to 0.16V At the minimum VDD condition, the operating frequency is 500Hz and the power consumption is 0.123W

Heterodimerization of Glycosylated Insulin-Like Growth Factor-1 Receptors and Insulin Receptors in Cancer Cells Sensitive to Anti-IGF1R Antibody

Identification of predictive biomarkers is essential for the successful development of targeted therapy. Insulin-like growth factor 1 receptor (IGF1R) has been examined as a potential therapeutic target for various cancers. However, recent clinical trials showed that anti-IGF1R antibody and chemotherapy are not effective for treating lung cancer.In order to define biomarkers for predicting successful IGF1R targeted therapy, we evaluated the anti-proliferation effect of figitumumab (CP-751,871), a humanized anti-IGF1R antibody, against nine gastric and eight hepatocellular cancer cell lines. Out of 17 cancer cell lines, figitumumab effectively inhibited the growth of three cell lines (SNU719, HepG2, and SNU368), decreased p-AKT and p-STAT3 levels, and induced G 1 arrest in a dose-dependent manner. Interestingly, these cells showed co-overexpression and altered mobility of the IGF1R and insulin receptor (IR). Immunoprecipitaion (IP) assays and ELISA confirmed the presence of IGF1R/IR heterodimeric receptors in figitumumab-sensitive cells. Treatment with figitumumab led to the dissociation of IGF1-dependent heterodimeric receptors and inhibited tumor growth with decreased levels of heterodimeric receptors in a mouse xenograft model. We next found that both IGF1R and IR were N-linked glyosylated in figitumumab-sensitive cells. In particular, mass spectrometry showed that IGF1R had N-linked glycans at N913 in three figitumumab-sensitive cell lines. We observed that an absence of N-linked glycosylation at N913 led to a lack of membranous localization of IGF1R and figitumumab insensitivity.The data suggest that the level of N-linked glycosylated IGF1R/IR heterodimeric receptor is highly associated with sensitivity to anti-IGF1R antibody in cancer cells

On-chip memory design in scaled technologies

In order to enhance performance and to support highly integrated functions, on-chip memory area has increased every technology generation. However, increased effect of parametric variations, susceptibility to soft errors, and increased leakage current in scaled technologies pose significant challenges in the design of low-power robust on-chip memory. In addition, there are application-specific design requirements. This research addresses the aforementioned issues related to on-chip memories to achieve robustness as well as optimality in terms of design requirements. Soft errors are especially important in Field Programmable Gate Arrays (FPGAs). In particular, soft errors in programming memory, leads to incorrect functionality in FPGAs. We present soft-error-tolerant FPGA operations using a new built-in 2-dimensional Hamming product code. Next, we propose a wide-range Voltage-Frequency-Scaling (VFS) Viterbi decoder using a novel traceback memory. Considering memory access patterns specific to Viterbi traceback, along with low-voltage array design, highly energy-efficient Viterbi decoder operation with wide-range of VFS is achieved. For general purpose computing, we first focus on on-chip SRAM cache design for energy-efficient high-performance operation. We present a 1R/1W multi-port 8T-SRAM array with column selection that enables supply-voltage-scalable set-associative caches with 1R/1W multi-port. The proposed technique addresses the limitation of a conventional 8T SRAM in which column selection prevents multi-port operation and vice versa. Finally, we consider Spin-Transfer Torque Magnetic RAM (STT-MRAM) as an alternative to SRAMs for future processors. A detailed analysis of energy-efficiency, area, and performance in comparisons to SRAM caches is carried out. It is shown that STT-MRAM cache has significant energy and performance benefits in low level cache hierarchy. In order to address excessive write-energy requirement of STT-MRAM, we propose a new cache architecture performing partial-line-update. The proposed architecture provides significant write-energy reduction, which can potentially make STT-MRAM suitable for on-chip caches

STT-MRAMs for Future Universal Memories: Perspective and Prospective

10.1109/MIEL.2012.622287228th International Conference on Microelectronics (MIEL)349-35

Spin-Transfer Torque MRAMs for Low Power Memories: Perspective and Prospective

10.1109/JSEN.2011.2124453IEEE SENSORS JOURNAL124756-76

Column-selection-enabled 8T SRAM array with ~1R/1W multi-port operation for DVFS-enabled processors

1

SHE-NVFF: Spin Hall Effect-Based Nonvolatile Flip-Flop for Power Gating Architecture

10.1109/LED.2014.2304683IEEE ELECTRON DEVICE LETTERS354488-49