We demonstrate a 10T subthreshold SRAM with an efficient bit-interleaving structure                 for soft-error tolerance and a differential read scheme for improved stability. The                 32kb (256128) SRAM array is fabricated in 90nm CMOS and operates at 31.25kHz at                 0.18V With more aggressive wordline boosting, the V DD can be reduced to 0.16V At                 the minimum VDD condition, the operating frequency is 500Hz and the power                 consumption is 0.123W

Chang, Ik Joon

Kim, Jae-Joon

Park, Sang Phill

Roy, Kaushik

English

Purdue E-Pubs

Purdue UniversityPurdue e-PubsDepartment of Electrical and ComputerEngineering Faculty PublicationsDepartment of Electrical and ComputerEngineeringJanuary 2008A 32kb 10T subthreshold SRAM array with bit-interleaving and differential read scheme in 90nmCMOSIk Joon ChangJae-Joon KimSang Phill ParkKaushik RoyFollow this and additional works at: http://docs.lib.purdue.edu/ecepubsThis document has been made available through Purdue e-Pubs, a service of the Purdue University Libraries. Please contact epubs@purdue.edu foradditional information.Chang, Ik Joon; Kim, Jae-Joon; Park, Sang Phill; and Roy, Kaushik, "A 32kb 10T subthreshold SRAM array with bit-interleaving anddifferential read scheme in 90nm CMOS" (2008). Department of Electrical and Computer Engineering Faculty Publications. Paper 9.http://dx.doi.org/http://dx.doi.org/10.1109/ISSCC.2008.4523220388 •  2008 IEEE International Solid-State Circuits ConferenceISSCC 2008 / SESSION 21 / SRAM / 21.721.7 A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOSIk Joon Chang1, Jae-Joon Kim2, Sang Phill Park1, Kaushik Roy11Purdue University, West Lafayette, IN,2IBM T.J. Watson, Yorktown Heights, NY For robust subthreshold SRAMs, 8T or 10T subthreshold SRAMsbased on single-ended read sensing have been proposed [1-3].While the schemes in [1-3] improve the read stability and writabil-ity significantly, their single-ended sensing methods still sufferfrom reduced bitline swing due to bitline noise. In addition, theprevious schemes do not have efficient bit-interleaving in the col-umn structure, which is critical to cope with multiple-bit softerrors [4]. In this paper, we present a 10T subthreshold SRAMwith efficient bit-interleaving for soft-error immunity and fullydifferential read for better stability. Figure 21.7.1 shows the 10T SRAM cell. In read mode, WL isenabled and VGND is forced to ground while W_WL remains dis-abled as shown in the timing diagram. Since the disabled W_WLmakes the nodes ‘Q’ and ‘QB’ isolated from the bitlines during theread mode, the read static noise margin (SNM) of this 10T SRAMis almost same as the hold SNM of conventional 6T SRAM. Duringthe write mode, both WL and W_WL are enabled to transfer thewrite data to cell node from the bitline. To compensate weakwritability, VWL and VW_WL are boosted by 33% of 0.3V VDD. Sincethe gate input boosting overwhelms the sizing effect in thesubthreshold region, we obtain strong writability without incur-ring a large area penalty in spite of having series transistors.Figure 21.7.1 shows 100mV boosting gives good writability even inthe worst-case process corner. To reduce the area overhead, fourcolumns share a common VGND node (Fig. 21.7.2). The pull-downstrength of VGND driver is degraded due to process variation, sothe dynamic-threshold MOS (DTMOS) technique is employed tomitigate this effect. The pull-down NMOS of the VGND driver isforward-biased during read, increasing the pull-down drivecurrent.As shown in the array structure in Fig. 21.7.2, WL is shared by thecells in a row and W_WL is shared by the cells in a column. Sinceboth WL and W_WL must be enabled to write a cell, each columnis selected individually depending on the value of W_WL. Thisunique feature can be used for bit-interleaving to reduce the mul-tiple-bit soft errors. Soft-error rate is expected to be significantlyhigher in subthreshold SRAM than that in super-threshold SRAMdue to the lower VDD and the smaller gate capacitance in sub-threshold region. Previous subthreshold SRAMs [1,2] do not allowbit-interleaving because the cells that are in the unselectedcolumns but share the wordline with the selected cells experiencesignificant stability degradation during write mode. Therefore, alogic word is composed of all cells sharing a wordline so that thedesign is exposed to multiple bit soft errors. (Fig. 21.7.3) On theother hand, in our technique, writing a cell does not affect hold sta-bility of other cells along the same wordline since W_WL is sharedby the cells in a column. When the W_WL of a column is raised forwriting a cell, W_WLs of other columns still stay at 0V. Hence, therise of WL does not affect hold stability of unwritten cells sharingthe WL. Monte-Carlo simulation results, shown in Fig. 21.7.3,show that the hold stability of unwritten cells sharing W_WL doesnot degrade during write. Despite the influence of enabled W_WLand VGND, the worst hold SNM shows improvement of 25%compared to conventional 6T SRAM since the pull-up of NMOStransistors (NL or NR) complements weak PMOS at FS processcorner, which is the worst case corner for hold stability. Since thehold stability in adjacent cells is not affected during write, bit-interleaving is efficiently implemented in our design, achievingsoft-error tolerance with conventional ECC [4].Another characteristic of our cell is the fully differential read,which improves the bitline noise immunity significantly duringread. The column structure in Fig. 21.7.4 explains the read mech-anism. When read begins, the wordline of the accessed SRAM cellsis raised and precharge signal (PRE_CH) is disabled. Dependingon the data value of the accessed cell, one of the precharged bit-lines (BL or BLB) starts discharging. The unfolded circuit dia-gram, which is equivalent to a column with the worst,case leakagecondition, is also shown in Fig. 21.7.4. During the read, the leak-age current through unselected cells (storing complementary valueto the accessed cell) impedes a successful read. In single-endedREAD structure, leakage makes it difficult to distinguish a logichigh and low from the developed bitline voltage [3]. Since a differ-ential read does not solely depend on the trip voltage of an invert-er, it is more tolerant to bitline leakage noise. We employ thedynamic DCVSL technique to further increase leakage tolerance.In Fig. 21.7.4, the discharge of BL turns on keeper M2 and bitlineleakage current in BLB is compensated by the drive current of M2.The graph in Fig. 21.7.4 shows the effectiveness of the DCVSL dif-ferential read. The simulation results show that 0.7VDD bitline dif-ferential  develops for 1024 cells per bitline at 25°C.In order to achieve larger bitline swing, read circuitry using cross-coupled inverters is included per each column. The footertransistor M0 of Fig. 21.7.4 prevents malfunction induced by intra-die variation inside the read circuitry. Drive current flowingthrough M0 is almost negligible before there is significant dis-charging from a bitline, excluding the influence of intra-dievariation inside the read circuitry. Leakage current through awrite driver reduces bitline swing, so to reduce this leakage,stacking transistors are employed (Fig. 21.7.4). Since a boostedsignal is used for W_WL and W_EN, degradation of write stabilityresulting from IR-drop of the stacked NMOS structure in the writedriver is almost negligible.An alternative 10T cell with differential bitlines can also be imple-mented by simply adding two read transistors and the complemen-tary bitline to the single-ended-read 8T cell [2]. That implementa-tion, however, does not allow bit-interleaving. The unique charac-teristic of our cell is to allow both bit-interleaving and differentialread with the same number of devices (10T) in a cell.The SRAM test-chip is fabricated in a 90nm CMOS technology(Fig. 21.7.7). For leakage comparison, 49kb arrays are implement-ed for both the conventional 6T cell and our 10T cell. Fig. 21.7.5shows that the leakage power consumption of our SRAM is close tothat of the 6T cell (between 0.96× and 1.1×) even though it hasextra transistors in a cell. This is because the subthreshold leak-age from the bitline to the cell node is drastically reduced by thestacking of devices in the leakage path. For performance andpower measurement, a 32kb (256×128) SRAM array is implement-ed using the cell. As shown in Fig. 21.7.6, the design operates at31.25kHz with a 0.18V supply and 33% boosted WL and W_WL.With more aggressive wordline boosting of 80mV, the VDD scalesdown to 0.16V. At 0.16V VDD, the operating frequency is 500Hz andpower consumption is 0.123μW.Acknowledgement: This research iss sponsored in part by SRC (1629.001) and by DARPA. Wethank Keejong Kim for integration of the design into a multi-project chip;Hyun-Joong Kim for helping wire-bonding; and Samsung ScholarshipFoundation.References:[1] B.H.Calhoun, A. Chandrakasan, “A 256kb Sub-Threshold SRAM in 65nmCMOS”, ISSCC Dig. Tech. Papers, pp.628-629, Feb. 2006.[2] N. Verma, A. Chandrakasan, “A 65nm 8T Sub-Vt SRAM EmployingSense-Amplifier Redundancy”, ISSCC Dig. Tech. Papers, pp.328-329, Feb.2006.[3] T. Kim, J. Liu, J. Keane, C. H. Kim, “A High-Density SubthresholdSRAM with Data-Independent Bitline Leakage and Virtual Ground ReplicaScheme”, ISSCC Dig. Tech. Papers, pp.330-331, Feb. 2006.[4] J. Maiz, S. Hareland, K. Zhang, and P. Armstrong, “Characterization ofMulti-bit Soft Error Events in Advanced SRAMs”, IEDM Dig. Tech.Papers,pp.21.4.1-21.4.4, Dec. 2003.978-1-4244-2011-7/08/$25.00 ©2008 IEEEPlease click on paper title to view Visual Supplement.Please click on paper title to view a Visual Supplement.389DIGEST OF TECHNICAL PAPERS  •Continued on Page 622ISSCC 2008 / February 5, 2008 / 4:45 PMFigure 21.7.1: Our 10T SRAM has almost same read SNM as the hold SNM ofconventional 6T SRAM. Boosted W_WL overcomes weak writability of conven-tional 6T in subthreshold.Figure 21.7.2: In our architecture, 4 columns have one common VGND node.W_WL is shared by cells in a column. For VGND driver, DTMOS technique isused.Figure 21.7.3: Writing a cell does not affect the hold stability of other cells inour design. Therefore, we can implement bit-interleaving structure.Figure 21.7.5: Leakage measurement result in 49kb 10T SRAM and 49kb con-ventional 6T. Figure 21.7.6: Test-chip measurement results. Minimum VDD is 160mV.Figure 21.7.4: Differential structure and dynamic DCVSL technique improvesbitline swing significantly. 21Please click on paper title to view Visual Supplement.Please click on paper title to view a Visual Supplement.622 •  2008 IEEE International Solid-State Circuits Conference 978-1-4244-2011-7/08/$25.00 ©2008 IEEEISSCC 2008 PAPER CONTINUATIONSFigure 21.7.7: Die micrograph and layout.Please click on paper title to view Visual Supplement.Please click on paper title to view a Visual Supplement.

A 32kb 10T subthreshold SRAM array with bit-interleaving and differential read scheme
            in 90nm CMOS

Ultra-low voltage operation of memory cells has become a topic of much interest due                 to its applications in very low energy computing and communications. However, due to                 parameter variations in scaled technologies, stable operation of SRAMs is critical                 for the success of low-voltage SRAMs. It has been shown that conventional 6T SRAMs                 fail to achieve reliable subthreshold operation. Hence, researchers have considered                 different configuration SRAMs for subthreshold operations having single-ended 8T or                 10T bit-cells for improved stability. While these bit-cells improve SRAM stability                 in subthreshold region significantly, the single-ended sensing methods suffer from                 reduced bit-line swing due to bit-line leakage noise. In addition, efficient                 bit-interleaving in column may not be possible and hence, the multiple-bit soft                 errors can be a real issue. In this paper, we propose a differential 10T bit-cell                 that effectively separates read and write operations, thereby achieving high cell                 stability. The proposed bit-cell also provides efficient bit-interleaving structure                 to achieve soft-error tolerance with conventional Error Correcting Codes (ECC). For                 read access, we employ dynamic DCVSL scheme to compensate bitline leakage noise,                 thereby improving bitline swing. To verify the proposed techniques, a 32 kb array of                 the proposed 10T bit-cell is fabricated in 90 nm CMOS technology. The hardware                 measurement results demonstrate that this bit-cell array successfully operates down                 to 160 mV. For leakage power comparison, we also fabricated 49 kb arrays of the 6T                 and the proposed 10T bit-cells. Measurement results show that the leakage power of                 the proposed bit-cell is close to that of the 6T (between 0.96x and 1.22x of             6T)

A 32 kb 10T sub-threshold sram array with bit-interleaving and differential read
            scheme in 90 nm CMOS

https://docs.lib.purdue.edu/cgi/viewcontent.cgi?article=1008&amp;context=ecepubs

A 32kb 10T subthreshold SRAM array with bit-interleaving and differential read scheme in 90nm CMOS

Abstract

Similar works

Full text

Available Versions

Purdue E-Pubs

Purdue E-Pubs