Low-power low-voltage chopped transconductance amplifier for noise and offset reduction

This paper describes the principle and design of a CMOS low-power, low-voltage, chopped transconductance amplifier, for noise and offset reduction in mixed analogue digital applications. The operation is based on chopping and dynamic element matching, to reduce noise and offset, without excessive increase of the charge injection residual offset. Experimental results show residual offsets of less than 150µV at 100kHz chopping frequency, a signal to noise ratio of 95dB, in audio band, for 100KHz chopping and a THD of -89dB. The power consumption is 594µW

A Two-stage approach to harmonic rejection mixing using blind interference cancelling

Current analog harmonic rejection mixers typically provide 30–40 dB of harmonic rejection, which is often not sufficient. We present a mixed analog-digital approach to harmonic rejection mixing that uses a digital interference canceler to reject the strongest interferer. Simulations indicate that, given a practical RF scenario, the digital canceler is able to improve the signal-to-interference ratio by 30–45 dB

Tunable n-path notch filters for blocker suppression: modeling and verification

N-path switched-RC circuits can realize filters with very high linearity and compression point while they are tunable by a clock frequency. In this paper, both differential and single-ended N-path notch filters are modeled and analyzed. Closed-form equations provide design equations for the main filtering characteristics and nonidealities such as: harmonic mixing, switch resistance, mismatch and phase imbalance, clock rise and fall times, noise, and insertion loss. Both an eight-path single-ended and differential notch filter are implemented in 65-nm CMOS technology. The notch center frequency, which is determined by the switching frequency, is tunable from 0.1 to 1.2 GHz. In a 50- environment, the N-path filters provide power matching in the passband with an insertion loss of 1.4–2.8 dB. The rejection at the notch frequency is 21–24 dB,P1 db> + 2 dBm, and IIP3 > + 17 dBm

Analysis of the high-speed polysilicon photodetector in fully standard CMOS technology

A high-performance lateral polysilicon photodiode was designed in standard 0.18 um CMOS technology. The device has a frequency bandwidth far in the GHz range: the measured bandwidth of the poly photodiode was 6 GHz, which gure was limited by the measurement equipment. The high intrinsic (physical) bandwidth is due to a short excess carrier lifetime. The external (electrical) bandwidth is also high because of a very small parasitic capacitance (<0.1 pF). This is the best bandwidth performance among all reported diodes designed in a standard CMOS. The quantum efficiency of this poly photodiode is 0.2% due to the very small light sensitive diode volume. The diode active area is limited by a narrow depletion region and its depth by the technology

A Blind Interference Canceling Technique for Two-Stage Harmonic Rejection in Down-mixers

This paper presents practical experiments on a harmonic rejection down-mixer, which offers up to 75 dB of harmonic rejection, without an RF filter. The down-mixer uses a two-stage approach; the first stage is an analog multi-path/multiphase harmonic rejection mixer followed by a second stage providing additional harmonic rejection based on blind adaptive interference canceling in the discrete-time domain. The aim is to show its functional operation. The canceler cannot cope with DC offsets. The DC offsets are removed by highpass filters. The signal paths used to obtain an estimate of the interference must be designed to provide as much attenuation of the desired signal as possible. Front-end nonlinearities and DC offsets are discussed

A Discrete-Time Mixing Receiver Architecture with Wideband Harmonic Rejection

A discrete-time mixing architecture for software-defined radio receivers exploits 8 RF voltage oversampling followed by charge-domain weighting to achieve 40dB 3rd and 5th harmonic rejection without channel bandwidth limitations. Noise folding is also reduced by 3dB. A zero-IF downconverter chip in 65nm CMOS can receive RF signals up to 900MHz, with NFmin=12dB, IIP3=11dBm at <20mW power consumption including multi-phase clock generation

Experimental Verification of a Harmonic-Rejection Mixing Concept using Blind Interference Canceling

Abstract—This paper presents the first practical experiments\ud on a harmonic rejection downconverter, which offers up to 75 dB of harmonic rejection, without an RF filter. The downconverter uses a two-stage approach; the first stage is an analog multipath/ multi-phase harmonic rejection mixer followed by a second stage providing additional harmonic rejection based on blind adaptive interference canceling in the discrete-time domain. The aim is to show its functional operation and to find practical performance limitations. Measurement results show that the harmonic rejection of the downconverter is insensitive to frontend nonlinearities and LO phase noise. The canceler cannot cope with DC offsets. The DC offsets are removed by highpass filters. The signal paths used to obtain an estimate of the interference must\ud be designed to provide as much attenuation of the desired signal as possible