A discrete-time mixing architecture for software-defined radio receivers exploits 8 RF voltage oversampling followed by charge-domain weighting to achieve 40dB 3rd and 5th harmonic rejection without channel bandwidth limitations. Noise folding is also reduced by 3dB. A zero-IF downconverter chip in 65nm CMOS can receive RF signals up to 900MHz, with NFmin=12dB, IIP3=11dBm at <20mW power consumption including multi-phase clock generation

Klumperink, E.A.M.

Nauta, B.

Ru, Z.

English

A discrete-time mixing architecture for software-defined radio receivers exploits 8 RF voltage oversampling followed by charge-domain weighting to achieve 40dB 3rd and 5th harmonic rejection without channel bandwidth limitations. Noise folding is also reduced by 3dB. A zero-IF downconverter chip in 65nm CMOS can receive RF signals up to 900MHz, with NFmin=12dB, IIP3=11dBm at &lt;20mW power consumption including multi-phase clock generation

Klumperink, Eric A.M.

Nauta, Bram

University of Twente Research Information

322 •  2008 IEEE International Solid-State Circuits ConferenceISSCC 2008 / SESSION 17 / WIDEBAND RECEIVERS / 17.1 17.1 A Discrete-Time Mixing Receiver Architecture with Wideband Harmonic RejectionZ. Ru, E.A.M. Klumperink, B. NautaUniversity of Twente, Enschede, NetherlandsRecently several CMOS software-defined radio (SDR) demonstra-tors have been presented using mixers as the wideband downcon-verter [1,2]. Meanwhile, the feasibility of RF samplers as down-converter has also been demonstrated [3,4]. These samplers allowfor more discrete-time (DT) and digital signal processing, and aretherefore better suited for advanced CMOS technologies.However, samplers suffer from several problems if used in a wide-band SDR. Charge sampling [3] gives a conversion gain which isinversely proportional to frequency [5]. Voltage sampling [4] does-n’t have this problem, but suffers from wideband noise folding. Inboth cases, RF pre-filters are needed to prevent interferersaround harmonics of the sampling clock from folding back to thebaseband. In this paper, we propose a DT harmonic-rejection(HR) mixing architecture that relaxes RF filter requirements andreduces the noise folding.The proposed SDR downconverter is aimed for the DVB-H stan-dard (470 to 862MHz) and for emerging cognitive radio applica-tions in the 200-to-900MHz band, which suffer from 3rd and 5thharmonic mixing. Figure 17.1.1 shows the architecture of the IC.An inverter-based RF-amplifier (RFA) drives a passive switched-capacitor (SC) core consisting of three stages. The first stage iseffectively an oversampler, with fs=8fc (fs is the sampling frequen-cy and fc is the carrier frequency). The second stage consists of I/QDT mixers for downconversion. The third stage is a low-pass IIRfilter. The zero-IF quadrature outputs are buffered via source fol-lowers. A clock generator is implemented using a divide-by-4 cir-cuit and NOR gates to generate 8-phase 12.5%-duty-cycle full-swing clocks to drive the sampling circuitry. An external sinu-soidal differential master clock is used with a frequency of 4fc.Note that an LNA is not included in this design.Figure 17.1.2 illustrates how the DT HR mixer works. Since thesampling rate is fs=8fc, the 7th harmonic folds to fc, and the 5th har-monic folds to 3fc, etc. Two DT I/Q mixers multiply the incomingsamples with a DT cosine and sine wave, i.e., weighting factors of1 and (1+√2) (cosine and sine with frequency fc sampled at 8fc).Since the DT clock is periodic, its spectrum only contains animpulse at fc. Multiplying the oversampled signal with the DTclock will downconvert the signal from fc to DC without foldingharmonics at 2fc, 3fc, and 4fc. However, the harmonics alreadyfolded to fc during the oversampling process cannot be differenti-ated from the wanted signal. These undistinguishable RF imagesare located at (k•n±1)fc (k=1,2,3…; and n=fs/fc). If n=8, the un-sup-pressed RF images are the 7th, 9th, 15th, 17th, … harmonics, but theproblematic 3rd and 5th harmonics are cancelled. The DT cosineand sine waves have a 90˚ phase difference, which, similar to acontinuous-time mixer, transfers the phase of the RF input signalto IF. In contrast to the case with an approximation by a timedelay [3,4], which is only exact for one frequency [5], the 90˚phase shift by DT I/Q mixing is frequency independent leading toa true wideband image rejection. Furthermore, the HR mixingalso suppresses noise around harmonics, and hence reduces noisefolding. In simulation, a 3dB NF improvement is observed, whichintuitively makes sense since half of the odd-order harmonic fold-ed noise components are suppressed.Figure 17.1.3 shows the SC core circuitry. For clarity only half ofthe fully differential system is shown. Eight interleaved samplingcells are controlled by 8-phase non-overlapping clocks, withCLKin for the sampling function and CLKout for the mixing func-tion. Each of the 8-phase clocks has a sample rate of fc, and alto-gether an effective sample rate of 8fc is achieved. In each sam-pling cell, there are two weighted sampling capacitors. To reliablymake an non-integer 1:(1+√2) ratio in layout is difficult. We useunit capacitor Csu with a 2:5 ratio as an approximation, which istheoretically sufficient for 35dB 3rd and 5th-order HR assuming 1˚phase error. Second-order effects such as charge sharing and gainroll-off can give several dBs extra. Although 5:12 would be moreaccurate, gain errors still don’t dominate over the phase errorsoriginating from clock timing mismatches. The DT mixing func-tion is implemented via a systematic combination of the outputswitches, to transfer charges from sampling capacitors to buffercapacitors (Cb). The charge sharing between the sampling andbuffer capacitors implements a low-pass IIR filter [3]. The out-puts can be decimated, e.g., via a moving average [3], to a lowersample rate and the next stages can use further DT signal pro-cessing as done in [3]. Figure 17.1.7 shows a micrograph of the chip that is fabricated ina 65nm CMOS process. The chip occupies an active area of0.36mm2. Figure 17.1.4 shows the measured gain and SSB NFover the RF band. At the low side, AC coupling limits the gain andat the high end the clock-circuitry speed limit of 3.6GHz isreached. Due to the varying gain, the SSB NF ranges from 12dBto 19dB, which is 20dB better than [4] and is the lowest amongall voltage-sampling mixers discussed in [6].In literature, a continuous-time HR mixer for transmitters is pro-posed in [7], and a 2MHz IF HR sampler in [8], both usingweighted amplifiers. We exploit weighted capacitors which canhave superior matching properties, and only need one RF ampli-fier, while still generating quadrature IF signals. The same num-ber of clock phases is needed for the proposed architecture andthat of [7] and [8], and therefore, there is no extra cost on clockspeed. A good HR ratio over a wide channel BW is important for wide-band standards and for future cognitive radio applications whichmight use multiple segments of free spectrum spreading over awide band. It is also important to reduce the distortions causedby strong out-of-channel interferes. In [8], the IF HR sampler isimplemented by summing the sampled data. This operation isequivalent to using a FIR filter to reject harmonics, which is onlyeffective for a limited channel BW due to the limited notch BWinherent in any FIR filter. DT mixing, however, does not have thislimitation. In Figure 17.1.5, the upper plot shows the HR ratio fora sampler using FIR filter drops significantly over the channel,while the proposed architecture gives wideband HR withoutchannel BW limitation. The trend of the measured results is ingood agreement with the simulated results. However, phase andgain mismatches limit the achievable HR ratio (not considered inthe simulation results).The lower plot in Figure 17.1.5 shows the measured results forthe HR ratio over the RF band, averaged over 10 chips (σ=5dB).On average, the 3rd-order HR ratio from 0.5 to 0.8GHz and the 5th-order HR ratio from 0.3 to 0.9GHz reach around 40dB, which iscomparable to the state-of-the-art continuous time HR mixer forRF receivers reported at only one frequency [1]. Figure 17.1.6 summarizes the measured parameters. The noiseand linearity performances are competitive with those of contin-uous-time mixers at reasonable power consumption, which showsthe feasibility of the proposed architecture for a practical receiv-er front-end. Acknowledgements:This work is funded by Freeband. We thank D. Leenaerts from NXP for helpwith chip fabrication, and G. Wienk and H. de Vries for valuable assistance.References:[1] R. Bagheri, A Mirzaei, S. Chehrazi et al, “An 800MHz to 5GHz Software-Defined Radio Receiver in 90nm CMOS,” ISSCC Dig. Tech. Papers, pp. 480-481,Feb. 2006.[2] J. Craninckx, M. Liu, D. Hauspie et al, “A Fully Reconfigurable Software-Defined Radio Transceiver in 0.13µm CMOS,” ISSCC Dig. Tech. Papers, pp. 346-347, Feb. 2007. [3] K. Muhammad, D. Leipold, B. Staszewski et al, “A Discrete-Time BluetoothReceiver in a 0.13µm Digital CMOS Process,” ISSCC Dig. Tech. Papers, pp. 268-269, Feb. 2004.[4] D. Jakonis, K. Folkesson, J. Dbrowski et al, “A 2.4-GHz RF SamplingReceiver Front-End in 0.18-µm CMOS,” IEEE J. Solid-State Circuits, vol. 40, no.6, pp. 1265-1277, Jun. 2005.[5] Z. Ru, E. Klumperink and B. Nauta, “On the Suitability of Discrete-TimeReceivers for Software-Defined Radio,” Proc. IEEE ISCAS, pp. 2522-2525, May2007.[6] H. Pekau and J. Haslett, “A 2.4 GHz CMOS Sub-Sampling Mixer withIntegrated Filtering,” IEEE J. Solid-State Circuits, vol. 40, no. 11, pp. 2159-2166, Nov. 2005.[7] J.A. Weldon, J.C. Rudell, L. Lin et al, “A 1.75GHz Highly-Integrated Narrow-Band CMOS Transmitter with Harmonic-Rejection Mixers,” ISSCC Dig. Tech.Papers, pp. 160-161, Feb. 2001.[8] A. Molnar, B. Lu, S. Lanzisera et al, “An Ultra-low Power 900 MHz RFTransceiver for Wireless Sensor Networks,” Proc. IEEE CICC, pp. 401-404, Oct.2004.©2008 IEEESession_17_Penmor.qxp:Session_  12/29/07  11:13 AM  Page 322323DIGEST OF TECHNICAL PAPERS  •Continued on Page 616ISSCC 2008 / February 5, 2008 / 1:30 PMFigure 17.1.1: Architecture of the HR sampling downconverter IC using the proposedDT mixing technique. All blocks are implemented on chip. Figure 17.1.2: Illustration of the DT harmonic-rejection mixing mechanism.Figure 17.1.3: Switched-capacitor core circuitry of the harmonic-rejection samplingdownconverter, with the clock scheme L0 to L7 shown in Fig. 17.1.1.Figure 17.1.5: Harmonic rejection ratio over channel and RF band. Figure 17.1.6: Measured key parameters.Figure 17.1.4: Gain and SSB NF over the RF band. Both gain and noise data are meas-ured at 1MHz IF.⇒11 2+1−1 2− − 1 2− −1−1 2+11sf⇒⇔CLKin CLKoutInputOutput1Output2CLKresSamplingCellOutput1Output2CLKin CLKoutCLKres2Csu5CsuInputL4L6L0 L5L7L1 From RF AmplifierCb CbI+ I- Q- Q+To IF Buffer To IF BufferCb CbSamplingCellSamplingCellL6L0L2SamplingCellL7L1L3SamplingCellL0L2L4SamplingCellL1L3L5SamplingCellL2L4L6SamplingCellL3L5L7SamplingCellRF path is differential0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9123456LO Frequency (GHz)Gain (dB)0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9101214161820LO Frequency (GHz)Noise Figure (dB)0 20 40 60 80 100102030405060Channel Frequency (MHz)HR Ratio (dB)3rd-order HR Ratio over Channel BW (LO@0.5GHz)0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.901020304050LO Frequency (GHz)HR Ratio (dB)Measured HR Ratio over RF Band (10-sample averaged)3rd order5th ordermeasured DT Mixingsimulated DT Mixingsimulated FIR Filtering Min: 12Max: 19SSB NF (dB)@ 1MHz IF250kHz1/f noise corner0.2 to 0.9FrequencyRange (GHz)+43dBmIIP2(503 & 504MHz)+11dBmIIP3(503 & 504MHz)Min: 1.7Max: 5.3Gain (dB)@ 1MHz IF10MHzIF bandwidthHarmonic-rejection ratio (10-sample averaged)Min: 32dBMax: 44dB5th-order(0.2 to 0.9GHz)Min: 32dBMax: 41dB3rd-order(0.2 to 0.9GHz)1.2VSupplyvoltageClock generator:7.8@0.2GHz LO10.6@0.9GHz LORFA & Buffer: 5.3Currentdrawn(mA)17Session_17_Penmor.qxp:Session_  12/29/07  11:13 AM  Page 323616 •  2008 IEEE International Solid-State Circuits Conference 978-1-4244-2010-0/08/$25.00 ©2008 IEEEISSCC 2008 PAPER CONTINUATIONSFigure 17.1.7: Micrograph of the chip fabricated in 65nm CMOS. The 0.36mm2 activearea includes all the blocks shown in Figure 17.1.1 and the bias current sources.Switched-Capacitor CoreBufferClockRFA1.2mm0.82mmBias0.82mm

A Discrete-Time Mixing Receiver Architecture with Wideband Harmonic Rejection

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A Discrete-Time Mixing Receiver Architecture with Wideband Harmonic Rejection

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