A Novel SAT-Based Approach to the Task Graph Cost-Optimal Scheduling Problem

The Task Graph Cost-Optimal Scheduling Problem consists in scheduling a certain number of interdependent tasks onto a set of heterogeneous processors (characterized by idle and running rates per time unit), minimizing the cost of the entire process. This paper provides a novel formulation for this scheduling puzzle, in which an optimal solution is computed through a sequence of Binate Covering Problems, hinged within a Bounded Model Checking paradigm. In this approach, each covering instance, providing a min-cost trace for a given schedule depth, can be solved with several strategies, resorting to Minimum-Cost Satisfiability solvers or Pseudo-Boolean Optimization tools. Unfortunately, all direct resolution methods show very low efficiency and scalability. As a consequence, we introduce a specialized method to solve the same sequence of problems, based on a traditional all-solution SAT solver. This approach follows the "circuit cofactoring" strategy, as it exploits a powerful technique to capture a large set of solutions for any new SAT counter-example. The overall method is completed with a branch-and-bound heuristic which evaluates lower and upper bounds of the schedule length, to reduce the state space that has to be visited. Our results show that the proposed strategy significantly improves the blind binate covering schema, and it outperforms general purpose state-of-the-art tool

Strengthening Model Checking Techniques with Inductive Invariants

This paper describes optimized techniques to efficiently compute and reap benefits from inductive invariants within SAT-based model checking. We address sequential circuit verification, and we consider both equivalences and implications between pairs of nodes in the logic networks. First, we present a very efficient dynamic procedure, based on equivalence classes and incremental SAT, specifically oriented to reduce the set of checked invariants. Then, we show how to effectively integrate the computation of inductive invariants within state-of-the-art SAT-based model checking procedures. Experiments (on more than 600 designs) show the robustness of our approach on verification instances on which stand-alone techniques fai

Circuit Based Quantification: Back to State Set Manipulation within Unbounded Model Checking

In this paper a non-canonical circuit-based state set representation is used to efficiently perform quantifier elimination. The novelty of this approach lies in adapting equivalence checking and logic synthesis techniques, to the goal of compacting circuit based state set representations resulting from existential quantification. The method can be efficiently combined with other verification approaches such as inductive and SAT-based pre-image verifications

A BMC-Formulation for the Scheduling Problem in Highly Constrained Hardware Systems

Abstract This paper describes a novel application for SAT-based Bounded Model Checking (BMC) within hardware scheduling problems. First of all, it introduces a new model for control-dependent systems. In this model, alternative executions (producing "tree-like" scheduling traces) are managed as concurrent systems, where alternative behaviors are followed in parallel. This enables standard BMC techniques, producing solutions made up of single paths connecting initial and terminal states. Secondly, it discusses the main problem arising from the above choice, i.e., rewriting resource bounds, so that they take into account the artificial concurrencies introduced for controlled behaviors. Thirdly, we exploit SAT-based Bounded Model Checking as a verification technique mostly oriented to bug hunting and counter-example extraction. In order to consider resource constraints, the solutions of modifying the SAT solver or adding extra clauses are both taken into consideration. Preliminary experimental results, comparing our SAT based approach to state-of-the art BDD-based techniques are eventually presented

S.Q.: A probabilistic and approximated approach to circuit-based formal verification

In both the hardware and the software domains, non-canonical circuit-based state set representations have recently been the subject of intensive investigations. One of the limiting factors of these representations has been the difficulty to control their size during key operations. For example, existentially and universally quantifying a variable implies doubling the circuit size in the worst case. In this paper, we present a probabilistic approach to keep under control the size of circuit-based representations when manipulating them. Every time a formula is becoming too cumbersome, we estimate it instead of building the exact result. The nature of the estimate, i.e., under- or over-approximation, depends on the problem that is being computed. The key idea of this process is to boost the expressiveness of the formula, delivering a dense representation, i.e., a formula compact in size but more expressive for the given verification problem. Experimental results show decisive reductions in terms of circuit size, and an increase in terms of density, i.e., the ratio between the cardinality of the on-set of a formula and the size of its representation. We applied the strategy to Bounded Model Checkingm, and circuit-based backward Unbounded Model Checking. We present experimental results from applying the approach to hard-to-solve verification instances. We observed speedups of more than one order of magnitude in some cases. Keywords: and-inverter graph, Boolean satisfiability, SAT-solvers, model checking, density, controllabilit

Guida alla programmazione in linguaggio C. Volume I: Fondamenti di programmazione

La seconda edizione presenta un aggiornamento dei contenuti allo scopo di rendere il testo più fedele ai programmi dei corsi di informatica di base del Politecnico di Torino così come strutturati recentemente. Questo ha comportato: 1. L'eliminazione degli argomenti relativi alla gestione dinamica della memoria, non più trattata nei corsi del primo anno. 2. L'eliminazione di alcuni esercizi di maggiore difficoltà logica. 3. La creazione, in ogni capitolo, di una sezione di esercizi proposti che estendono quelli precedentemente risolti e costituiscono un'ottima base per un approccio autonomo al "problem solving". La soluzione di tutti gli esercizi, tanto quelli "risolti" (la cui soluzione è già presentata nel testo), quanto quelli "proposti", è inclusa nel materiale elettronico associato al volume. Tale materiale, invece di essere fornito su CD, come nella versione precedente, è reso disponibile tramite il sito WEB dell'editore

Guida alla programmazione in linguaggio C. Volume I: Fondamenti di programmazione

La seconda edizione presenta un aggiornamento dei contenuti allo scopo di rendere il testo più fedele ai programmi dei corsi di informatica di base del Politecnico di Torino così come strutturati recentemente. Questo ha comportato: 1. L'eliminazione degli argomenti relativi alla gestione dinamica della memoria, non più trattata nei corsi del primo anno. 2. L'eliminazione di alcuni esercizi di maggiore difficoltà logica. 3. La creazione, in ogni capitolo, di una sezione di esercizi proposti che estendono quelli precedentemente risolti e costituiscono un'ottima base per un approccio autonomo al "problem solving". La soluzione di tutti gli esercizi, tanto quelli "risolti" (la cui soluzione è già presentata nel testo), quanto quelli "proposti", è inclusa nel materiale elettronico associato al volume. Tale materiale, invece di essere fornito su CD, come nella versione precedente, è reso disponibile tramite il sito WEB dell'editore