A multiple in-camera processing system for machine vision.

In a typical machine vision application, a line-scan camera positioned on the production line captures images of the parts to be inspected and sends them to the machine vision computer. The computer then uses high-speed data acquisition devices and sophisticated analysis software to extract information from these cameras and generates decisions about the product and manufacturing system. As the manufacturing systems increasingly generate more fine featured and advanced products, the need for higher resolution and faster processing of these camera images is necessary to maintain quality control. To reduce the overwhelming amount of data from multiple camera systems to the analysis computer, an in-camera processing system is introduced. This system involves placing a computing system inside the camera which can perform similar operations to the analysis system, but without all of the additional overhead components. The work presented in this thesis describes an enhanced embedded system which is mounted into a DALSA line-scan camera. This system provides support for real-time one dimensional signal processing with the aid of integrated hardware and software resources.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis1999 .M89. Source: Masters Abstracts International, Volume: 40-03, page: 0757. Adviser: Graham A. Jullien. Thesis (M.Sc.)--University of Windsor (Canada), 1999

Difficult operations in the multi-dimensional logarithmic number system.

The Multi-Dimensional Logarithmic Number System (MDLNS), with similar properties to the Logarithmic Number System (LNS), provides more degrees of freedom than the LNS by virtue of having two or more orthogonal bases and the ability to use multiple digits. Unlike the LNS there is no direct functional relationship between binary/floating point representation and the MDLNS representation. Traditionally look-up tables (LUTs) were used to move from the binary domain to the MDLNS domain. This method could be unrealistic for hardware implementation when large binary ranges or multiple digits were used. The lack of this direct relationship also complicated the addition and subtraction operations in MDLNS. Again LUTs were used to perform these operations but they could become unrealistically large when multiple digits or large index ranges were used. The work presented in this thesis describes efficient techniques for implementing difficult MDLNS operations such as binary to MDLNS conversion as well as addition and subtraction. These techniques require the use of a new memory device with range addressing capabilities, a RALUT (range addressable look-up table). The RALUT reduces the exponential complexity associated with the traditional use of potentially large LUTs by physically removing redundant hardware used to store the MDLNS conversion, addition, and subtraction information. Other significant MDLNS improvements such as choosing efficient and optimal bases, the one-bit sign architecture, and single-digit MDLNS RALUT reduction are also discussed. These improvements are shown to reduce the hardware implementation and improve performance without sacrificing any of the MDLNS accuracy.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis2003 .M87. Source: Dissertation Abstracts International, Volume: 65-01, Section: B, page: 0365. Adviser: Graham Arnold Jullien. Thesis (Ph.D.)--University of Windsor (Canada), 2003

Digit-Level Serial-In Parallel-Out Multiplier Using Redundant Representation for a Class of Finite Fields

Two digit-level finite field multipliers in F2m using redundant representation are presented. Embedding F2m in cyclotomic field F2(n) causes a certain amount of redundancy and consequently performing field multiplication using redundant representation would require more hardware resources. Based on a specific feature of redundant representation in a class of finite fields, two new multiplication algorithms along with their pertaining architectures are proposed to alleviate this problem. Considering area-delay product as a measure of evaluation, it has been shown that both the proposed architectures considerably outperform existing digit-level multipliers using the same basis. It is also shown that for a subset of the fields, the proposed multipliers are of higher performance in terms of area-delay complexities among several recently proposed optimal normal basis multipliers. The main characteristics of the postplace&route application specific integrated circuit implementation of the proposed multipliers for three practical digit sizes are also reported

A Low-Power Two-Digit Multi-dimensional Logarithmic Number System Filterbank Architecture for a Digital Hearing Aid

This paper addresses the implementation of a filterbank for digital hearing aids using a multi-dimensional logarithmic number system (MDLNS). The MDLNS, which has similar properties to the classical logarithmic number system (LNS), provides more degrees of freedom than the LNS by virtue of having two, or more, orthogonal bases and the ability to use multiple MDLNS components or digits. The logarithmic properties of the MDLNS also allow for reduced complexity multiplication and large dynamic range, and a multiple-digit MDLNS provides a considerable reduction in hardware complexity compared to a conventional LNS approach. We discuss an improved design for a two-digit 2D MDLNS filterbank implementation which reduces power and area by over two times compared to the original design

PCB Fabricated Passive RF Balun for 3 T MRI Applications

In this article, a passive balun for 3 T magnetic resonance imaging (MRI) scanners operating at 128 MHz was designed and analyzed to successfully convert a balanced input signal from a dipole/loop antenna into an unbalanced output signal connected to preamplifiers or transmission line. The lumped circuit element, mathematical modeling and simulations and measurement results for the balun performance are shown. The proposed balun is intended to be integrated in electric and magnetic field probes for time domain monitoring of the time-varying RF signals during medical device testing. The implemented balun is fabricated on a low-cost, copper cladded, four-layer FR4 printed circuit board (PCB) with overall footprint of 13.4 mm × 14 mm. A comparison among the ADS momentum simulations and the measured results indicates good agreement with the measured insertion and return losses of better than -1.5 dB and -15 dB, respectively

A Non-Magnetic RF Balun Designed at 128 MHz Centre frequency for 3 T MRI Scanners

In this work, a non-magnetic RF balun is implemented for 3 T magnetic resonance imaging (MRI) scanners operating at 128 MHz to transform a balanced input signal from a dipole or loop antenna into an unbalanced output signal. It is fabricated on a low-cost, copper cladded four-layer printed circuit board (PCB), FR4 with a thickness of 1.57 mm and a copper thickness of 35 ?m, with overall footprint of 11.6 mm × 12.2 mm. A comparison among the ADS RF momentum simulations and the measured results indicates a good agreement with the measured insertion and return losses of better than -1 dB and -13 dB, respectively, in a 50 ? termination setting