Caractérisation des mosfets en silicium à budget thermique réduit pour applications numériques et haute fréquence sur des systèmes d'intégration séquentielle 3D

3D sequential integration (3DSI) consists of sequentially stacking active device layers using vertical interconnections with similar dimensions as standard Back-End-Of-Line contacts (<100nm). It allows the co-integration of different systems on separated layers with a high interconnection density and it eliminates costly trade-offs coming from the optimization of different devices on the same substrate. Likewise, the reduced interconnection parasitic and heterogeneous integration offer great potential for 5G millimeter-wave (mmW) applications.However, 3D stacked devices come along with new process challenges. Top-tier transistors need to be processed at low temperatures (≤ 500°C) to preserve the integrity of devices on lower tiers. Standard CMOS integration with low thermal budget (LTB) leads to substantial performance degradation. Nevertheless, new breakthroughs in the silicon LTB integration process open the path to the development of devices that reach the same performance of their high temperature counterparts. Therefore, the objective of this Ph.D. work is to analyze the effects of those new processes on the electrical characteristics of LTB MOSFET devices and draw guidelines for further optimization.The manuscript for this Ph.D. introduces the main results obtained from the recent development of this technology and it is presented on three parts:Activation of source and drain dopants near the junction using a low temperature Solid State Epitaxy Recrystallization (SPER) anneal. The study is performed with an estimation of the junction profile using a novel nondestructive CV technique coupled to as improved conformal mapping model of the transistors fringe capacitances. The results are used to understand the electrical behavior and degradation mechanisms of the devices as function of the overlap position.Trapping properties of the low permittivity material (SiCO) used for the low temperature gate spacer oxide and its effects on the transistor performance. Two trapping mechanisms are identified on this material: Fast Silicon interface traps, related to the quality of the native oxide, and slow deep defects distributed in the bulk of the SiCO oxide. The effect of those traps near the access region of the electrical performance transistor are studied.Effect of key low temperature process steps of the devices RF FoMs. The objective is to evaluate the performance of the devices at high frequencies. The lower parasitic capacitances from SiCO spacers, low gate resistance from the UV nanoseconds laser anneal and high mobility from the CESL tensile stain are key low thermal budget steps contributing to high-performance RF transistors with similar FoMs to HTB counterparts.L'intégration séquentielle en 3D (3DSI) consiste à empiler de manière séquentielle des couches de dispositifs actifs à l'aide de connexions verticales ayant des dimensions similaires à celles des contacts standard Back-End-Of-Line (<100 nm). Cela permet la co-intégration de différents systèmes sur des couches séparées avec une densité d'interconnexion élevée et élimine les compromis coûteux liés à l'optimisation de différents dispositifs sur le même substrat. De même, la réduction des parasites d'interconnexion et l'intégration hétérogène offrent un grand potentiel pour les applications 5G à ondes millimétriques (mmW).Cependant, les dispositifs empilés en 3D présentent de nouveaux défis de processus. Les transistors de haut niveau doivent être traités à basse température (≤ 500 °C) pour préserver l'intégrité des dispositifs sur les niveaux inférieurs. L'intégration CMOS standard avec un faible budget thermique (LTB) entraîne une dégradation importante des performances. Néanmoins, de nouvelles avancées dans le processus d'intégration LTB du silicium ouvrent la voie au développement de dispositifs atteignant les mêmes performances que leurs homologues à haute température. Par conséquent, l'objectif de ce travail de doctorat est d'analyser les effets de ces nouveaux processus sur les caractéristiques électriques des dispositifs MOSFET LTB et d'établir des lignes directrices pour une optimisation ultérieure.Le manuscrit de cette thèse présente les principaux résultats obtenus grâce au récent développement de cette technologie et est présenté en trois parties :Activation des dopants de la source et du drain près de la jonction à l'aide d'un recuit d'épitaxie à l'état solide à basse température (SPER). L'étude est réalisée en estimant le profil de la jonction à l'aide d'une nouvelle technique de CV non destructive couplée à un modèle amélioré de cartographie conforme des capacités marginales des transistors. Les résultats sont utilisés pour comprendre le comportement électrique et les mécanismes de dégradation des dispositifs en fonction de la position de chevauchement.Propriétés de piégeage du matériau de permittivité faible (SiCO) utilisé pour l'oxyde d'espacement de grille à basse température et ses effets sur les performances du transistor. Deux mécanismes de piégeage sont identifiés sur ce matériau : les pièges d'interface en silicium rapides, liés à la qualité de l'oxyde natif, et les défauts profonds lents répartis dans le volume de l'oxyde SiCO. L'effet de ces pièges près de la région d'accès des performances électriques du transistor est étudié.Effet des principales étapes de processus à basse température sur les figures de mérite RF des dispositifs. L'objectif est d'évaluer les performances des dispositifs à des fréquences élevées. Les capacités parasites plus faibles des espacesurs SiCO, la résistance de grille réduite grâce au recuit laser aux nanosecondes UV et la mobilité élevée grâce à la contrainte de tension CESL sont des étapes clés à faible budget thermique contribuant à des transistors RF haute performance avec des figures de mérite similaires à celles des homologues à budget thermique élevé (HTB)

On the Zero Temperature Coefficient in FD-SOI MOSFETs

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Capacitance RF Characterization and Modeling of 28 FD-SOI CMOS Transistors down to Cryogenic Temperature

International audienceThis paper investigates the capacitance characterization and modeling of CMOS transistor integrated in Fully Depleted Silicon On Insulator (FD-SOI) technology from room temperature down to 4.2K. RF capacitances of transistors with different gate lengths are carefully extracted as a function of temperature and modeled. We highlight the impact of the carrier freeze-out in the substrate on the transistor capacitance

Miniaturization of Transmission Lines: Meandered Slow-wave CPWs

International audienceThis work presents novel transmission line structures based on Meandered Slow-wave CoPlanar Waveguides (MS-CPWs), aiming to achieve high miniaturization. As a proof-of-concept, these two kinds of transmission lines were designed and fabricated in the AMS 0.35 mu m CMOS technology together with classical straight and meandered microstrip lines. Measurement results from 70 kHz to 100 GHz of the fabricated transmission lines are presented. At 80 GHz, all the considered transmission lines present similar quality factors, ranging between 10 and 14. On the other hand, at this frequency, one of the developed MS-CPW presents an effective dielectric constant of 88, while the meandered microstrip exhibits an equivalent effective dielectric constant of 51, thus leading to higher compactness for the MS-CPW

Experimental Analysis and Modeling of Self-Heating and Thermal Coupling in 28 nm FD-SOI CMOS Transistors Down to Cryogenic Temperatures

International audienceThermal effects are a major concern for efficient cryoCMOS circuit design. This work presents an experimental analysis of self-heating effect and thermal propagation in FD-SOI technology, measured from room temperature (300K) down to 4.2K, using the gate resistance thermometry technique. The channel temperature increase and the in-plane temperature profile were investigated and analytically modeled, together with thermal coupling between simultaneously operating devices. We demonstrated a major constraint for extremely low temperature operation due to abrupt channel temperature rise even at sub-1mW input power, which propagates over hundreds of nanometers along the Si layer. Thermal coupling was identified as a source for self-heating aggravation, and needs to be particularly optimized to limit the heating of cryo-circuits

Ultra-fast CV methods (< 10µs) for interface trap spectroscopy and BTI reliability characterization using MOS capacitors

International audienceTwo Ultra-Fast capacitance characterization methods based on the displacement current measure are explored for MOS capacitance devices. The first method measure the variation of charge obtained from several 100ns short pulses while the second uses a (1 to 5&micro;s/V) continuous ramp to perform the capacitance measurement. Different applications are investigated for each method depending on measurement time and precision. The short pulsed method is used to perform a CV trap spectroscopy. Thanks to distinctive charging and discharging phases we are able to separately extract the capture and emission behavior of interface traps. We demonstrate that BTI characterization can be performed on simple MOScap using CV measurements based on IV ramp as in MOSFET devices. Furthermore, both methods can be combined in oxides presenting a high hysteresis behavior, to separately characterize low frequency oxide trapping from high frequency interface state trapping.</p

Key low temperature processes for a silicon-based 3D sequential integration

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Statistical and electrical modeling of FDSOI four-gate qubit MOS devices at room temperature

International audienceThis paper presents an electrical characterization and a compact modeling of FD-SOI fourgate qubit MOS devices, carried out at room temperature and in linear regime. The main figures ofmerit are extracted from average drain current curves using Y – function method. Poisson solver-based simulations are performed to interpret the experimental data, in particular the influence among gates and the effective channel length modulation. Furthermore, a drain current matching analysis between gates is conducted, and the main variability parameters are extracted. Our results, despite the unconventional device engineering, show a variability performance comparable to the state-of-the-art 28nm FD-SOI technology. Finally, a Lambert function based model is developed to validate both the electrical and statistical characterization. It is assumed, according to the experimental data, that the four gate device can be modeled as the series of four identical and independent transistors. Including the contribution of source and drain access resistance it has been possible to reproduce the device behavior at high external gates voltages

Key low temperature processes for a silicon-based 3D sequential integration

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Record RF Performance (ft=180GHz and fmax=240GHz) of a FDSOI NMOS processed within a Low Thermal Budget for 3D Sequential Integration

International audienceRecord RF Figure-Of-Merits (FoM) is highlighted for a 42nm NMOS transistor fully processed at Low Thermal Budget (LTB) (&lt;500&deg;C) needed for 3D Sequential Integration (3DSI). f T =180GHz &amp; f MAX =240GHz are reported at V DD =0.9V; which is actually very similar to performance of reference Si MOSfets processed with a Hot Thermal Budget (HTB) (Fig. 15). This excellent result was possible thanks to a careful optimization of the LTB process after an advanced characterization and modeling of key technological parameters such as mobility, Gate-Capacitance and Gate resistance</p