Mismatch-Shaped Pseudo-Passive Two-Capacitor DAC

A simple mismatch-shaping scheme is proposed for a two-capacitor DAC. Unlike in other mismatchshaping systems, the shaped error is generated by direct filtering of a well-defined bounded signal, which can be generated as white noise. The operation is closely related to a specific digital interpolation filter, but arbitrary properties of the overall interpolation characteristic can be assured. Simulations indicate that the scheme can be used for the realization of DACs with 16-bit linearity and SNR performance, with only 0.1 % capacitance accuracy. The DAC is pseudo-passive, i.e. an active element is required only to buffer the output signal. Hence, it is potentially a very low-power circuit, suitable for portable applications

Digitally Synthesized Stochastic Flash ADC Using Only Standard Digital Cells

It is demonstrated in this paper that it is possible to synthesize a stochastic flash ADC entirely from Verilog code and a standard digital library. An analog comparator is introduced that is constructed from two cross-coupled 3-input digital NAND gates, and can be described in Verilog. The synthesized comparators have random, Gaussian offsets that are used as virtual voltage references to make a flash ADC. A piecewise-linear inverse Gaussian CDF function is used to correct the nonlinearity introduced by the Gaussian offset distribution. The prototype IC is fabricated in 90nm CMOS and implements a 2047-comparator version of the proposed architecture. All components including the comparators, the ones adder, and the piecewise inverse Gaussian function are all implemented in Verilog. Conventional digital synthesis and place-and-route is then used to generate the physical layout, making this the first fully synthesized ADC. SNDR of 35.9dB (without calibration) is achieved at 210MSPS from the Verilog synthesized design.This is an author's peer-reviewed final manuscript, as accepted by the publisher. The published article is copyrighted by IEEE-Institute of Electrical and Electronics Engineers and can be found at: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=8919]. ©201X IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.Keywords: Circuit synthesis, Analog-digital conversion, Stochastic system

The Analysis and Application of Redundant Multi-stage ADC Resolution Improvements Through PDF Residue Shaping

An analysis of the statistics of multi-stage (pipeline, SAR and algorithmic) ADCs with redundancy is performed and the ability to achieve an extra 6dB of resolution in ADCs with half-bit redundancy is shown due to probability density function (PDF) residue shaping. This paper classifies redundancy techniques to show that only some have properties leading to statistical resolution improvements. When properly implemented, resolution gains are maintained even in the presence of large sub-ADC non-linearity. ADC design criteria for maximizing these resolution increases through PDF residue shaping are described including improved back-end ADCs, stage comparator offset bounds, and the use of scaled conventional restoring with Z added levels (CRZ) stage redundancy. PDF residue shaped structural improvements are also quantified in relation to ideal and non-ideal traditional multi-stage ADC structures.Keywords: Algorithmic ADC, Error correction, Redundancy resolution improvement, Multi-stage ADC, SAR redundancy, Residue shaping, Pipeline redundanc

A Multiplexer-Based Digital Passive Linear Counter (PLINCO)

A ones adder is an important circuit block that is required in many varying applications. This work proposes a design that largely relies on passive transmission-gate multiplexers. Many variations are suggested that can inherently generate a thermometer coded output or one-hot encoded output. The proposed structure has area and power that increases with order n² for a n number of inputs. A folding technique is then suggested that reduces the area/power to order n log(n). The folded PLINCO also has a cell-based structure that aids in layout and makes it possible to be added to a digital standard cell library.Keywords: digital circuits, thermometer code, low power, ones adderKeywords: digital circuits, thermometer code, low power, ones adde

Ring Amplifiers for Switched Capacitor Circuits

In this paper the fundamental concept of ring amplification is introduced and explored. Ring amplifiers enable efficient amplification in scaled environments, and possess the benefits of efficient slew-based charging, rapid stabilization, compression-immunity (inherent rail-to-rail output swing), and performance that scales with process technology. A basic operational theory is established, and the core benefits of this technique are identified. Measured results from two separate ring amplifier based pipelined ADCs are presented. The first prototype IC, a simple 10.5-bit, 61.5dB SNDR pipelined ADC which uses only ring amplifiers, is used to demonstrate the core benefits. The second fabricated IC presented is a high-resolution pipelined ADC which employs the technique of Split-CLS to perform efficient, accurate amplification aided by ring amplifiers. The 15-bit ADC is implemented in a 0.18 μm CMOS technology and achieves 76.8 dB SNDR and 95.4 dB SFDR at 20 Msps while consuming 5.1 mW, achieving a FoM of 45 fJ/conversion-step.Keywords: correlated level shifting, analog to digital conversion, analog to digital converter, slew-based, RAMP, rail-to-rail, ring amplification, ADC, CLS, ringamp, A/D, low power, ring amp, scaling, Split-CLS, ring amplifier, high resolution, switched-capacitor, scalability, stabilized ring oscillator, nanoscale CMOSThis is the author's peer-reviewed final manuscript, as accepted by the publisher. The published article is copyrighted by IEEE-Institute of Electrical and Electronics Engineers and can be found at: http://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=4. ©2012 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works

Linearity improvement technique for CMOS continuous-time filters

A linearity improvement technique using a combination of passive resistors and current-steering MOS transistors as a variable resistance element is applied in the implementation of low-distortion continuous-time filters in complementary metal-oxide-semiconductor (CMOS) technology. This work is motivated by the fact that to date, most of the techniques in continuous-time, electronically tunable filters perform quite poorly in linearity. The proposed technique relies on the linearity of the passive resistors and the tunability of the current-steering MOS transistors operating in the triode region. By novel application of systematic feedback loops and by placing the nonlinear elements inside the feedback, the distortion resulting from the nonlinear devices is greatly reduced by the filter loop gain. Theoretical and experimental results, in agreement, show a significant improvement in linearity. For an audio-band (22-kHz) fifth-order Bessel filter implementation, linearity better than $-$90 dB THD is demonstrated given a 2 kHz, 4 V\sb{p-p} signal in a 5-V system. The filter implementation includes a simple and novel automatic frequency-tuning method, which employs a switched-capacitor reference resistor instead of applying a conventional phase-locked loop technique or its variations. Also included in the filter implementation is a linear programming approach to optimize the dynamic range, under the constraint of a fixed capacitor area that is assumed to be the dominant factor in the total chip area.U of I OnlyETDs are only available to UIUC Users without author permissio

A Note From the Editors

This editorial describe the genesis of the first special issue for the IEEE TCAS-II, highlighting the specific features of a special issue made of short papers onl