Current-Processing Current-Controlled Universal Biquad Filter

This paper presents a current-processing current-controlled universal biquad filter. The proposed filter employs only two current controlled current conveyor transconductance amplifiers (CCCCTAs) and two grounded capacitors. The proposed configuration can be used either as a single input three outputs (SITO) or as three inputs single output (TISO) filter. The circuit realizes all five different standard filter functions i.e. low-pass (LP), band-pass (BP), high-pass (HP), band-reject (BR) and all-pass (AP). The circuit enjoys electronic control of quality factor through the single bias current without disturbing pole frequency. Effects of non-idealities are also discussed. The circuit exhibits low active and passive sensitivity figures. The validity of proposed filter is verified through computer simulations using PSPICE

Adiabatic Approach for Low-Power Passive Near Field Communication Systems

This thesis tackles the need of ultra-low power electronics in the power limited passive Near Field Communication (NFC) systems. One of the techniques that has proven the potential of delivering low power operation is the Adiabatic Logic Technique. However, the low power benefits of the adiabatic circuits come with the challenges due to the absence of single opinion on the most energy efficient adiabatic logic family which constitute appropriate trade-offs between computation time, area and complexity based on the circuit and the power-clocking schemes. Therefore, five energy efficient adiabatic logic families working in single-phase, 2-phase and 4-phase power-clocking schemes were chosen. Since flip-flops are the basic building blocks of any sequential circuit and the existing flip-flops are MUX-based (having more transistors) design, therefore a novel single-phase, 2-phase and 4-phase reset based flip-flops were proposed. The performance of the multi-phase adiabatic families was evaluated and compared based on the design examples such as 2-bit ring counter, 3-bit Up-Down counter and 16-bit Cyclic Redundancy Check (CRC) circuit (benchmark circuit) based on ISO 14443-3A standard. Several trade-offs, design rules, and an appropriate range for the supply voltage scaling for multi-phase adiabatic logic are proposed. Furthermore, based on the NFC standard (ISO 14443-3A), data is frequently encoded using Manchester coding technique before transmitting it to the reader. Therefore, if Manchester encoding can be implemented using adiabatic logic technique, energy benefits are expected. However, adiabatic implementation of Manchester encoding presents a challenge. Therefore, a novel method for implementing Manchester encoding using adiabatic logic is proposed overcoming the challenges arising due to the AC power-clock. Other challenges that come with the dynamic nature of the adiabatic gates and the complexity of the 4-phase power-clocking scheme is in synchronizing the power-clock v phases and the time spent in designing, validation and debugging of errors. This requires a specific modelling approach to describe the adiabatic logic behaviour at the higher level of abstraction. However, describing adiabatic logic behaviour using Hardware Description Languages (HDLs) is a challenging problem due to the requirement of modelling the AC power-clock and the dual-rail inputs and outputs. Therefore, a VHDL-based modelling approach for the 4-phase adiabatic logic technique is developed for functional simulation, precise timing analysis and as an improvement over the previously described approaches

Flux free growth of large FeSe1/2Te1/2 superconducting single crystals by an easy high temperature melt and slow cooling method

We report successful growth of flux free large single crystals of superconducting FeSe1/2Te1/2 with typical dimensions of up to few cm. The AC and DC magnetic measurements revealed the superconducting transition temperature (Tc) value of around 11.5K and the iso-thermal MH showed typical type-II superconducting behavior. The lower critical field being estimated by measuring the low field iso-thermal magnetization in superconducting regime is found to be above 200 Oe at 0K.Comment: 15 pages text + Figs. Novel large cm size FeSe1/2Te1/2 superconducting crystal

Adiabatic Flip-Flops and Sequential Circuit Design using Novel Resettable Adiabatic Buffers

We propose novel resettable adiabatic buffers for five adiabatic logic families namely; Efficient Adiabatic Charge Recovery Logic (EACRL), Improved Efficient Charge Recovery Logic (IECRL), Positive Feedback Adiabatic Logic (PFAL), Complementary Pass-transistor Adiabatic Logic (CPAL) and Clocked Adiabatic Logic (CAL). We present the design of resettable flip-flops using the proposed buffers. The proposed flip-flops alleviate the problem of increased energy and area consumption incurred by the existing mux-based resettable flip-flops. We then design the 3-bit up-down counters and extended our comparison beyond energy dissipation using the above five adiabatic logic families. PFAL based sequential circuit designs gives the best performance trade-offs in terms of complexity, energy, speed and area compared to the other adiabatic designs