149 research outputs found

    Max-log demapper architecture design for DVB-T2 rotated QAM constellations

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    International audience— Rotated and cyclic-Q delayed (RCQD) quadrature amplitude modulation (QAM) improve DVB-T2 system performance over highly time-frequency selective channels. However, when compared with conventional QAM demapper, the RCQD demapper requires a higher computational complexity. In this paper, a complexity-reduced max-log demapper is derived and implemented over a FPGA platform. The proposed demapper allows to find the maximum likelihood (ML) point with a search spanning only M signal constellation points and guarantees to obtain the same log-likelihood ratio (LLR) metrics as the optimum max-log soft decision demapper while spanning at most 2 M signal constellation points. The optimized hardware implementation introduces only a slight performance loss compared to the floating-point full complexity max-log performance. Index Terms — DVB-T2, Rotated and Cyclic Q Delayed (RCQD) Constellations, Log-Likelihood Ratio (LLR), Max-Log Demapper

    Bayesian estimation of human impedance and motion intention for human-robot collaboration

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    This article proposes a Bayesian method to acquire the estimation of human impedance and motion intention in a human-robot collaborative task. Combining with the prior knowledge of human stiffness, estimated stiffness obeying Gaussian distribution is obtained by Bayesian estimation, and human motion intention can be also estimated. An adaptive impedance control strategy is employed to track a target impedance model and neural networks are used to compensate for uncertainties in robotic dynamics. Comparative simulation results are carried out to verify the effectiveness of estimation method and emphasize the advantages of the proposed control strategy. The experiment, performed on Baxter robot platform, illustrates a good system performance

    Multiple Second-Order Generalized Integrators Based Comb Filter for Fast Selective Harmonic Extraction

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    Fast and accurate harmonic extraction plays a vital role in power quality assessment, grid synchronization, harmonic compensation, etc. This paper proposes a multiple second-order generalized integrators (SOGIs) based comb filter (SOGIs-CF) for fast selective harmonic extraction. Compared with the conventional multiple SOGI-quadrature signal generators (SOGI-QSGs) scheme, the tedious harmonic decoupling network (HDN) is removed off without sacrificing steady-state detection accuracy, and thus the computation burden can be reduced. In addition, the parameters design criteria and the digital implementation issues have been discussed in detail. Finally, the experimental results confirm the fast response and high detection accuracy of the proposed scheme. The characteristic of fast harmonic magnitude signal detection makes the proposed method quite suitable for the realization of flexible output capacity-limit control of multifunction inverters

    Multirate Resonant Controllers for Grid-Connected Inverters with Harmonic Compensation Function

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    Modeling and control of LCL-filtered grid-tied inverters with wide inductance variation

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    A New Tuning Method of Multi-Resonant Current Controllers for Grid-Connected Voltage Source Converters

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    A shuffled iterative bit-interleaved coded modulation receiver for the DVB-T2 standard: Design, implementation and FPGA prototyping

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    International audienceRotated QAM constellations improve Bit-Interleaved Coded Modulation (BICM) performance over fading channels. Indeed, an increased diversity is obtained by coupling a constellation rotation with interleaving between the real and imaginary components of transmitted symbols either in time or frequency domain. Iterative processing at the receiver side can provide additional improvement in performance. In this paper, an efficient shuffled iterative receiver is investigated for the second generation of the terrestrial digital video broadcasting standard DVB-T2. Scheduling an efficient message passing algorithm with low latency between the demapper and the LDPC decoder represents the main contribution. The design and the FPGA prototyping of the resultant shuffled iterative BICM receiver are then described. Architecture complexity and measured performance validate the potential of iterative receiver as a practical and competitive solution for the DVB-T2 standard

    Passivity-Based Design of Repetitive Controller for LCL-Type Grid-Connected Inverters Suitable for Microgrid Applications

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    Rethinking the competition between detection and ReID in Multi-Object Tracking

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    Due to balanced accuracy and speed, joint learning detection and ReID-based one-shot models have drawn great attention in multi-object tracking(MOT). However, the differences between the above two tasks in the one-shot tracking paradigm are unconsciously overlooked, leading to inferior performance than the two-stage methods. In this paper, we dissect the reasoning process of the aforementioned two tasks. Our analysis reveals that the competition of them inevitably hurts the learning of task-dependent representations, which further impedes the tracking performance. To remedy this issue, we propose a novel cross-correlation network that can effectively impel the separate branches to learn task-dependent representations. Furthermore, we introduce a scale-aware attention network that learns discriminative embeddings to improve the ReID capability. We integrate the delicately designed networks into a one-shot online MOT system, dubbed CSTrack. Without bells and whistles, our model achieves new state-of-the-art performances on MOT16 and MOT17. Our code is released at https://github.com/JudasDie/SOTS
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