Determinants for the success of regional ICT ventures: a close examination of south korea

Background This study identifies the key motivational factors in enhancing economic performance and increasing new job opportunities for information and communication technology ventures (ICTVs) in South Korea and examines their potential causal relationships through structural equation modeling analysis on data collected from over 200 ICTVs located in Daedeok Innopolis. Results The results indicate that the economic performance of ICTVs is determined mainly by government support, innovation effort, and private equity and support. Government support and innovation effort are also positively associated with new job opportunities. Conclusions The theoretical, industrial implications of the key findings, and recommendations for the Korean government are discussed.This work was supported by the National Research Foundation of Korea Grant funded by the Korean Government (NRF-2014S1A5A2A01011769). This study was also supported by the Dongguk University Research Fund of 2015

A Potentiostat Readout Circuit with a Low-Noise and Mismatch-Tolerant Current Mirror Using Chopper Stabilization and Dynamic Element Matching for Electrochemical Sensors

This paper presents a potentiostat readout circuit with low-noise and mismatch-tolerant current mirror using chopper stabilization and dynamic element matching (DEM) for electrochemical sensors. Current-mode electrochemical sensors are widely used to detect the blood glucose and viruses in the diagnosis of various diseases such as diabetes, hyperlipidemia, and the H5N1 avian influenza virus (AIV). Low-noise and mismatch-tolerant characteristics are essential for sensing applications that require high reliability and high sensitivity. To achieve these characteristics, a proposed potentiostat readout circuit is implemented using the chopper stabilization scheme and the DEM technique. The proposed potentiostat readout circuit consists of a chopper-stabilized programmable gain transimpedance amplifier (TIA), gain-boosted cascode current mirror, and a control amplifier (CA). The chopper scheme, which is implemented in the TIA and CA, can reduce low frequency noise components, such as 1/f noise, and can obtain low-noise levels. The mismatch offsets of the cascode current mirror can be reduced by the DEM operation. The proposed current-mirror-based potentiostat readout circuit is designed using a standard 0.18 μm CMOS process and can measure the sensor current from 350 nA to 2.8 μA. The input-referred noise integrated from 0.1 Hz to 1 kHz is 21.7 pARMS, and the power consumption was 287.9 μW with a 1.8 V power supply

Current-Feedback Instrumentation Amplifier Using Dual-Chopper Fill-In Technique

In this study, we describe a dual-chopper glitch-reduction current-feedback instrumentation amplifier (CFIA) with a ripple reduction loop. The amplifier employs the chopping technique to reduce low-frequency noise, such as 1/f noise. A glitch caused by chopping occurs at each chopper clock edge and results in intermodulation distortion (IMD). Owing to the input offset, the chopping technique also produces ripples. In this study, the glitch-induced IMD was reduced using a fill-in technique whereby only neat signals were alternately used as outputs by avoiding the glitch section with dual-chopping channel CFIA. To avoid using a high-order, low-frequency filter, a ripple reduction loop was implemented to reduce the ripple generated by chopping. The CFIA is based on a low-noise chopper fully differential difference amplifier with a cascode stage and a Monticelli-class AB output stage, which can drive a larger load and increase power efficiency. The proposed dual-chopper CFIA was fabricated using a 0.18 µm CMOS standard process, and its current consumption with a 1.8-V power supply is 29.5 μA. The proposed CFIA has a gain of 51 V/V, input referred noise of 53.3 nV/√Hz at 1 Hz, and a noise efficiency factor of 4.48

Low-Noise Potentiostat Readout Circuit with a Chopper Fully Differential Difference Amplifier for Glucose Monitoring

This paper presents a low-noise potentiostat readout circuit with a chopper fully differential difference amplifier (FDDA) for glucose monitoring. Glucose monitoring is necessary for the early diagnosis of diabetes complications and for health management. Ammeter electrochemical sensors are widely used for glucose detection, and in general, a three-electrode structure of a reference electrode (RE), a counter electrode (CE), and a working electrode (WE) is implemented with a potentiostat structure. A low-noise characteristic of the readout circuit is essential for highly accurate glucose monitoring. The chopping technique can reduce low-frequency noises such as 1/f noise and can achieve the required low-noise characteristic. The proposed potentiostat readout circuit is based on a low-noise chopper FDDA with a class-AB output stage. The implementation of the chopper FDDA scheme of the potentiostat readout circuit can decrease the number of amplifiers in the control part of the potentiostat, with reduced power consumption and a wide dynamic output range. The negative feedback loop of the inverting amplifier scheme with the FDDA maintains the voltage between the WE and RE constants. The negative feedback loop tracks the reference voltage of the RE with an input voltage of the WE. The proposed potentiostat readout circuit is designed in the standard 0.18 µm CMOS process, and the simulated current consumption is 48.54 μA with a 1.8 V power supply. The simulated input-referred noise level was 8.53 pArms

A Single-Bit Incremental Second-Order Delta-Sigma Modulator with Coarse-Fine Input Buffer

This paper presents an incremental second-order delta-sigma modulator with a coarse-fine input buffer in 180-nm CMOS. The modulator’s architecture was implemented as a second-order cascade of integrators with a feedback structure. The switched-capacitor integrator was operated in discrete time, with high-gain amplifiers required to achieve improved performance during the integration phase. The amplifier comprised rail-to-rail input and gain-boosted cascode intermediate stages, thus achieving a high gain and wide input voltage range. The circuit adopts a coarse-fine buffer for higher performance. The coarse buffer is operated first to enable fast settling through a high slew rate, followed by the fine buffer to satisfy the low-noise and high-accuracy characteristics. The fine buffer has a smaller current consumption with higher power efficiency. The experiment results show that the proposed input buffer achieved a 13.14 effective number of bits and an 80.87 dB signal-to-noise and distortion ratio. The modulator operates a single bit and sampling clock at 125 kHz. The proposed delta-sigma modulator was operated at 1.8 V. The proposed circuit was designed using a standard 0.18-μm CMOS process with an active area of 1.06 mm2. The total current consumption with the coarse-fine buffer was 1.374 mA

Low-Noise Potentiostat Readout Circuit with a Chopper Fully Differential Difference Amplifier for Glucose Monitoring

This paper presents a low-noise potentiostat readout circuit with a chopper fully differential difference amplifier (FDDA) for glucose monitoring. Glucose monitoring is necessary for the early diagnosis of diabetes complications and for health management. Ammeter electrochemical sensors are widely used for glucose detection, and in general, a three-electrode structure of a reference electrode (RE), a counter electrode (CE), and a working electrode (WE) is implemented with a potentiostat structure. A low-noise characteristic of the readout circuit is essential for highly accurate glucose monitoring. The chopping technique can reduce low-frequency noises such as 1/f noise and can achieve the required low-noise characteristic. The proposed potentiostat readout circuit is based on a low-noise chopper FDDA with a class-AB output stage. The implementation of the chopper FDDA scheme of the potentiostat readout circuit can decrease the number of amplifiers in the control part of the potentiostat, with reduced power consumption and a wide dynamic output range. The negative feedback loop of the inverting amplifier scheme with the FDDA maintains the voltage between the WE and RE constants. The negative feedback loop tracks the reference voltage of the RE with an input voltage of the WE. The proposed potentiostat readout circuit is designed in the standard 0.18 µm CMOS process, and the simulated current consumption is 48.54 μA with a 1.8 V power supply. The simulated input-referred noise level was 8.53 pArms

Low-Noise, Low-Power Readout IC for Two-Electrode ECG Recording Using Common-Mode Charge Pump for Robust 20-V_PP Common-Mode Interference

A low-noise and -power readout integrated circuit (IC) for two-electrode electrocardiogram (ECG) recording is developed in this study using a common-mode charge pump (CMCP) for a robust 20-VPP common-mode interference (CMI). Two-electrode ECG recording offers more comfort than three-electrode ECG recording. Contrasting to the three-electrode ECG recording, the two-electrode ECG recording is affected by CMI during measurements; the intervention of a large CMI will distort the ECG signal measurement. To achieve robustness for the CMI, the proposed ECG readout IC adopts CMCP—it uses switched capacitors that store and subtract CMI by control logic. In this paper, a window comparator structure is applied to CMCP to obtain a signal with less distortion. The window voltage ranges were set between the input common-mode ranges in which IA can operate. Therefore, a signal with less distortion was obtained by stopping the operation of CMCP between the window voltage ranges. It also reduced additional current consumption. To achieve this, the proposed circuit is implemented using a chopper stabilization technique. The chopper implemented in the amplifier can reduce low-frequency noise components, such as 1/f noise, and it comprises a CMCP, current feedback instrumentation amplifier, QRS peak detector, relaxation oscillator, voltage reference, timing generator, and serial peripheral interface on a single chip. The proposed circuit was designed using a standard 0.18 μm CMOS process with an active area of 0.54 mm2. The proposed CMCP achieves a CMI robustness of 20 VPP at 60 Hz. The measured input-referred noise level was 119 nV/√Hz at 1 Hz, and the power consumption was 23.83 μW with a 1.8 V power supply

Optimized renewable and sustainable electricity generation systems for Ulleungdo Island in South Korea

The South Korean government has long been attempting to reduce the nation’s heavy reliance on fossil fuels and increase environmental safety by developing and installing renewable power generation infrastructures and implementing policies for promoting the green growth of Korea’s energy industry. This study focuses on the use of independent renewable power generation systems in the more than 3000 officially affirmed islands off Korea’s coast and proposes a simulated solution to the electricity load demand on Ulleungdo Island that incorporates several energy sources (including solar, batteries, and wind) as well as one hydro-electric and two diesel generators. Recommendations based on the simulation results and the limitations of the study are discussed