Architectures Flexibles pour la Validation et L'exploration de Réseaux-sur-Puce

For A multiprocessor system-on-chip (MPSOC), the communication backbone is a central component of prime importance. This is due to the importance of the communications on such distributed systems. Now that networks-on-chip (NoCs) are admitted to be the solution which theoretically best solves the problem of on-chip communications, an important problem which rises consists in providing the designer with fast validation techniques able to tackle such complexes systems. Indeed, despite their regular architectures networks-in-chip internal interactions are difficult to formalize. On the other side, classical validation approaches are far from being suited for NoC-based systems due to their lack of flexibility and scalability. This thesis introduces a new concept in the field of hardware validation of networkson- chip; we have called this new concept “Inaccurate Hardware Emulation” in contrast with most hardware emulation approaches which assume a “cycle accurate bit accurate” precision. Our approach inherits from all advantages of hardware prototyping on reconfigurable devices and adds new scalability features. Study conducted during this thesis showed that under the non-congested regime a NoC may admit a number of alterations on its characteristics (introduced by the emulation platform) without adopting a completely different behavior. The multi-FPGA emulation technique proposed in this thesis is highly flexible since it relies on serial inter-FPGA interconnections. Serial interconnections are less sensitive to noises than parallel style of interconnections, and allow then for higher transfer rates. On the other hand, our emulation approaches does not poses any constraint on the emulation speed. If we consider the fact that serial interconnection schemes may introduce additional delays and the high speeds of the emulation process, performance of the NoC being emulated on the multi-FPGA emulator may deviate from the original NoC. We have studied this phenomenon and we have proposed various solutions for it.L'infrastructure de communication pour un système multiprocesseur mono-puce (MPSoC) est un organe central et de première importance. Cette importance s'explique par la place importante que tiennent les communications dans de tels systèmes distribués. Alors qu'il est maintenant admis que les réseaux -sur-puce (NoCs) constituent une solution théoriquement idéale, il se pose le problème de la validation de telles architectures complexes. En effet, malgré la régularité de leurs architectures, les réseaux-sur-puce restent des systèmes dont les interactions internes sont très difficiles à appréhender. Par ailleurs, les approches de validation classiquement employées sont très mal adaptées aux systèmes à base de NoC car très peu flexibles et très peu scalables. Cette thèse introduit un nouveau concept dans la validation matérielle des réseauxsur- puce, ce concept que nous avons appelé « émulation imprécise » contraste avec les approches d'émulation matérielles classiques qui sous-entendent toutes une précision au « cycle près, bit près ». Notre approche hérite de tous les avantages liés au prototypage matériel sur les plateformes reconfigurables et y ajoute un degré de flexibilité très élevé. En effet, l'étude menée au cours de ce travail sur le comportement des réseaux -sur-puce à commutation de paquets en régime non congestionné montre que, sous certaines conditions, des modifications des caractéristiques du NoC (introduites par la plateforme d'émulation elle même) peuvent être tolérées sans que pour autant le comportement du réseau ne change de façon radicale. La technique d'émulation multi-FPGA étudiée dans cette thèse est une technique très flexible car basée sur un mode d'interconnexions inter-FPGA série. Les interconnexions séries sont beaucoup moins sensibles aux phénomènes de parasitage que les interconnexions parallèles et par conséquent les vitesses de transferts sont beaucoup plus élevées. D'autre part la technique d'émulation que nous proposons ne pose aucune condition sur la vitesse du processus d'émulation lui-même. Considérant les délais additionnels induits pas les liaisons séries et les vitesses d'émulation très élevées, un phénomène de déviation des performances peut être observé d'où l'imprécision de l'émulation. Ce phénomène a été étudié dans le cadre de cette thèse et nous avons proposé plusieurs solutions afin d'y remédier.Mots cles : MEMS RF, interrupteur, modelisation, modele statistique, test, evaluation, regression lineaire

Scalable Multi-FPGA Platform for Networks-On-Chip Emulation

ISBN : 978-1-4244-1027-4International audienceInterconnect validation is an important early step toward global SoC (System-On-Chip) validation. Fast performances evaluation and design space exploration for NoCs (Networks-On-Chip) are therefore becoming critical issues. A significant speedup of the global validation process for NoC-centric SoCs could be achieved by prototyping such systems on reconfigurable devices (FPGA). However, as SoC complexity increases with the technology scaling, existing general purpose prototyping platforms are far from being suited for large systems. In this paper we present a study for a scalable multi-FPGA platform, designed for NoCs emulation and debugging. This platform allows the integration of complete systems as well as a near cycleaccurate performance estimation

Networks-In-Package: Performances management and design methodology

ISBN : 978-1-4244-1616-5International audienceNowadays large scale MPSoC designs embedding multiple processors, memories and specialized IPs require high integration densities which can not be met at an acceptable cost within the standard single-chip technology. The systems-in-package (SiP) approach has been proposed then as an alternative which enables such integration requirements. Even though analysis of systems-in-package design techniques shows large similarities with standard techniques for multi-chip-modules (MCM), there is a huge methodological lack for communication-centric MPSoCs. In this paper we motivate the need for new design methodologies which addresses the various problems of the emerging NiP (networks-in- package) paradigm with a special focus on performances considerations. We also propose a complete NoC architecture (MS-NoC) and a design flow aimed at helping designers to build NiP architectures

Large Scale On-Chip Networks : An Accurate Multi-FPGA Emulation Platform

ISBN : 978-0-7695-3277-6International audienceInterconnect validation is an important early step toward global SoC (System-On-Chip) validation. Fast performances evaluation and design space exploration for NoCs (Networks-On-Chip) are therefore becoming critical issues. A significant speed up of the global validation process for NoC-centric SoCs could be achieved by prototyping such systems on reconfigurable devices (FPGA). However, as SoC complexity increases with the technology scaling, existing general purpose prototyping platforms are far from being suited for large systems. In this paper we present a study for a scalable multi-FPGA platform, designed for NoCs emulation and debugging. This platform allows the integration of complete systems as well as a near cycle-accurate performance estimation

Multi-CPU/FPGA Platform Based Heterogeneous Multiprocessor prototyping: New Challenges for Embedded Software Designers

ISBN : 978-0-7695-3180-9International audienceHeterogeneous Multiprocessor Systems on-Chip (MPSoC) are considered to be the next generation of multiprocessor architectures able to deal with the ever increasing performances and scalability demands. In fact, combining heterogeneous processors in the same architecture allows drawing on strength from each kind of processor, increasing overall system performance and efficiency. However, such a design introduces new challenges, especially for embedded software designers. Multi-CPU/FPGA platform based prototyping approach is an attractive solution for fast validation of MPSoC's embedded software. We address in this paper, the difficulty of ensuring an efficient bridging between processors in heterogeneous MPSoC. We propose a common FPGA based middleware structure to manage communication and synchronisation between the processors. Then, we describe a semi-systematic design space exploration framework for automatic inter-processor communication and synchronization refinement

Self-Organisation : Paradigms and Applications

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Self-Organising Applications: A Survey

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Self-Organising Applications: A Survey

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