High-field current transport and charge trapping in buried oxide of SOI materials under high-field electron injection, Journal of Telecommunications and Information Technology, 2004, nr 1

Mechanisms of the charge transfer, the charge trapping, and the generation of positive charge during the high-field electron injection into buried oxide of silicon-on-insulator structures fabricated by different technologies are analyzed based on the data obtained from current-voltage, injection current-time, and capacitance-voltage characteristics together with SIMS data. Electron injection both from the Si film and the Si substrate is considered. The possibility of using the trap-assisted electron tunneling mechanisms to explain the high-field charge transfer through the buried oxides of UNIBOND and SIMOX SOI materials is considered. It is shown that considerable positive charge is accumulated near the buried oxide/substrate interface independently from the direction of the injection (from the lm or from the silicon substrate) for UNIBOND and SIMOX SOI structures. Thermal stability of the charge trapped in the buried oxides is studied at temperatures ranging from 20 to 400C. The theory is compared with the experimental data to find out the mechanisms of the generation of positive charge in UNIBOND and SIMOX buried oxides

Charge-pumping characterization of SOI devices fabricated by means of wafer bonding over pre-patterned cavities, Journal of Telecommunications and Information Technology, 2007, nr 3

The quality of the silicon-buried oxide bonded interface of SOI devices created by thin Si film transfer and bonding over pre-patterned cavities, aiming at fabrication of DG and SON MOSFETs, is studied by means of chargepumping (CP) measurements. It is demonstrated that thanks to the chemical activation step, the quality of the bonded interface is remarkably good. Good agreement between values of front-interface threshold voltage determined from CP and I-V measurements is obtained

Design and fabrication of silicon-on-silicon-carbide substrates and power devices for space applications

A new generation of power electronic semiconductor devices are being developed for the benefit of space and terrestrial harsh-environment applications. 200-600 V lateral transistors and diodes are being fabricated in a thin layer of silicon (Si) wafer bonded to silicon carbide (SiC). This novel silicon-on-silicon-carbide (Si/SiC) substrate solution promises to combine the benefits of silicon-on-insulator (SOI) technology (i.e device confinement, radiation tolerance, high and low temperature performance) with that of SiC (i.e. high thermal conductivity, radiation hardness, high temperature performance). Details of a process are given that produces thin films of silicon 1, 2 and 5 μm thick on semi-insulating 4H-SiC. Simulations of the hybrid Si/SiC substrate show that the high thermal conductivity of the SiC offers a junction-to-case temperature ca. 4× less that an equivalent SOI device; reducing the effects of self-heating, and allowing much greater power density. Extensive electrical simulations are used to optimise a 600 V laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET) implemented entirely within the silicon thin film, and highlight the differences between Si/SiC and SOI solutions

The effect of interfacial charge on the development of wafer bonded silicon-on-silicon-carbide power devices

A new generation of power electronic semiconductor devices are being developed for the benefit of space and terrestrial harsh-environment applications. 200-600 V lateral transistors and diodes are being fabricated in a thin layer of silicon (Si) wafer bonded to semi-insulating 4H silicon carbide (SiC) leading to a Si/SiC substrate solution that promises to combine the benefits of silicon-on-insulator (SOI) technology with that of SiC. Here, details of a process are given to produce thin films of silicon 1 and 2 μm thick on the SiC. Simple metal-oxide-semiconductor capacitors (MOS-Cs) and Schottky diodes in these layers revealed that the Si device layer that had been expected to be n-type, was now behaving as a p-type semiconductor. Transmission electron microscopy (TEM) of the interface revealed that the high temperature process employed to transfer the Si device layer from the SOI to the SiC substrate caused lateral inhomogeneity and damage at the interface. This is expected to have increased the amount of trapped charge at the interface, leading to Fermi pinning at the interface, and band bending throughout the Si layer

Characterization of Carrier Generation in Thin-Film SOI Devices By Reverse Gated-Diode Technique and Its Application At High Temperatures

This paper presents a revision of the reverse gated-diode technique for application to thin-film SOI devices. Based on modeling of gate-controlled volume and surface generation components, a reliable approach for extracting generation parameters in thin-film SOI devices from reverse gated-diode measurements is developed and validated for high temperatures. The proposed approach is used for characterizing generation processes and evaluating generation parameters in UNIBOND SOI devices operating at high temperatures (in the temperature range 100 – 300° C)

Study of the positive charge buildup into buried oxide of SIMOX SOI structure during bias-temperature stress

The buildup of fixed and mobile charge in the buried oxide (BOX) of silicon implanted by oxygen (SIMOX) silicon-on-insulator (SOI) structures during bias-temperature (BT) cycling has been studied by the thermally stimulated polarization (TSP) current technique and C-V measurements. Two polarization processes have been observed: the first process with activation energy of 0.3 eV is likely related to the positively charged ion transport across the BOX, the second process with activation energy about 1.2 eV is associated with space charge polarization. It was found that the ion transport is created simultaneously with the process of lateral positive charge buildup near the BOX/substrate interface when the bias is applied to the structure at temperatures above 280oC

Gm/Id Method for Threshold Voltage Extraction Applicable in Advanced MOSFETs with nonlinear behavior above threshold

A method is proposed for determining the threshold voltage in a MOSFET, based on the derivative of the gm/Id ratio with respect to the gate voltage, which theoretically originates from the unified charge-control model similar to the capacitance-derivative method. This yields threshold voltages significantly less affected by gate-voltage-dependent mobility and series resistance than linear-extrapolation techniques. Moreover, it is more physically adequate in the case of advanced MOSFETs with ultrathin dielectrics, thin SOI body, or double gate operation, featuring a gradual transition from the exponential to linear charge control. The robustness of the method is experimentally verified on FinFETs with different lengths