Behavioral Modeling of IC Ports Including Temperature Effects

The development of temperature-dependent macromodels for digital IC ports is addressed. The proposed modeling approach is based on the theory of discrete-time parametric models and allows one to estimate the model parameters from voltage and current waveforms observed at the ports and to implement the model as a SPICE subcircuit. The proposed technique is validated by applying it to commercial devices described by detailed transistor-level models. The obtained models perform at a good accuracy level and are more efficient than the original transistor-level models

Macromodeling strategy for digital devices and interconnects

International audienceThis paper proposes a macromodeling approach for the simulation of digital interconnected systems. Such an approach is based on a set of macromodels describing IC ports, IC packages and multiconductor interconnect structures in standard circuit simulators, like SPICE. We illustrate the features of the macromodels and we demonstrate the proposed approach on a realistic simulation problem

Macromodeling of Digital I/O Ports for System EMC Assessment

This paper addresses the development of accurate and efficient behavioral models of digital integrated circuit input and output ports for EMC and signal integrity simulations. A practical modeling process is proposed and applied to some example devices. The modeling process is simple and efficient, and it yields models performing at a very high accuracy leve

Parametric Macromodels of Drivers for SSN Simulations

This paper addresses the modeling of output and power supply ports of digital drivers for accurate and efficient SSN simulations. The proposed macromodels are defined by parametric relations, whose parameters are estimated from measured or simulated port transient responses, and are implemented as SPICE subcircuits. The modeling technique is applied to commercial high-speed devices and a realistic simulation example is shown

Macromodeling of Digital I/O Ports for System EMC Assessment

behavioral models of digital integrated circuit input and output ports for EMC and signal integrity simulations. A practical modeling process is proposed and applied to some example devices. The modeling process is simple and efficient, and it yields models performing at a very high accuracy level

First- and

second-level packaging for the IBM eServer z900 This paper describes the system packaging of the processor cage for the IBM eServer z900. This server contains the world’s most complex multichip module (MCM), with a wiring length of 1 km and a maximum power of 1300 W on a glass-ceramic substrate. The z900 MCM contains 35 chips comprising the heart of the central electronic complex (CEC) of this server. This MCM was implemented using two different glass-ceramic technologies: one an MCM-D technology (using thin film and glass-ceramic) and the other a pure MCM-C technology (using glass-ceramic) with more aggressive wiring ground rules. In this paper we compare these two technologies and describe their impact on the MCM electrical design. Similarly, two different board technologies for the housing of the CEC are discussed, and the impact of their electrical properties on the system design is described. The high-frequency requirements of this design due to operating frequencies of 918 MHz for on-chip and 459 MHz for off-chip interconnects make a comprehensive design methodology and post-routing electrical verification necessary. The design methodology, including by H. Harre