Actor-oriented control system design: A responsible framework perspective

Complex control systems are heterogeneous, in the sense of discrete computer-based controllers interacting with continuous physical plants, regular data sampling interleaving with irregular communication and user interacting, and multilayer and multimode control laws. This heterogeneity imposes great challenges for control system design in terms of end-to-end control performance modeling and simulation, traceable refinements from algorithms to software/hardware implementation, and component reuse. This paper presents an actor-oriented design methodology that tackles these issues by separating the data-centric computational components (a.k.a. actors) and the control-flow-centric scheduling and activation mechanisms (a.k.a. frameworks). Semantically different frameworks are composed hierarchically to manage. heterogeneous models and achieve actor and framework reuse. We introduce a notion of responsible frameworks to characterize the property that a framework can aggregate individual actor's execution into a well-defined composite execution such that heterogeneous models can be composed. This methodology is implemented in the Ptolemy II software environment. We discuss how some of the most useful models for control system design are implemented as responsible frameworks. As an example, the methodology and the Ptolemy II software environment is applied to the design of a distributed, real-time software implementation of a pendulum inversion,and stabilization system

High-level system synthesis and optimization of dataflow programs for MPSoCs

The growing complexity of digital signal processing applications make a compelling case the use of high-level design and synthesis methodologies for the implementation on reconfigurable and embedded devices. Past research has shown that raising the level of abstraction of design stages does not necessarily gives penalties in terms of performance or resources. Dataflow programs provide behavioral descriptions capable of expressing both sequential and parallel algorithms and enable natural design abstractions, modularity, and portability. In this paper, a tool implementing dataflow programs onto embedded heterogeneous platforms by means of high-level synthesis, software synthesis and interface synthesis is presented for MPSoCs platfroms

Dataflow programs analysis and optimization using model predictive control techniques: An example of bounded buffer scheduling

This paper presents a new approach to buffer dimensioning for dynamic dataflow implementations. A novel transformation applied to the execution trace graph of a dataflow program is introduced in order to generate an event driven system. It is shown how model predictive control theory techniques can be applied to such a system to analyse the execution space of a dataflow program and to define and to minimize a bounded buffer size configuration that corresponds to a deadlock free execution. Some experimental results obtained using two design examples, i.e. a JPEG and an MPEG HEVC decoder, are reported and compared to the state of the art results in order to show the effectiveness of the introduced approach

Partitioning And Optimization Of High Level Stream Applications For Multi Clock Domain Architectures

In this paper we propose a design methodology to partition dataflow applications on a multi clock domain architecture. This work shows how starting from a high level dataflow representation of a dynamic program it is possible to reduce the overall power consumption without impacting the performances. Two different approaches are illustrated, both based on the post-processing and analysis of the causation trace of a dataflow program. Methodology and experimental results are demonstrated in an at-size scenario using an MPEG-4 Simple Profile decoder

Multi-clock domain optimization for reconfigurable architectures in high-level dataflow applications

This paper proposes a new design methodology to partition streaming applications onto a multi clock domain architecture. The objective is to save power by running different parts of the application at the lowest possible clock frequency that will not violate the throughput requirements. The solution involves partitioning the application into an appropriate number of clock domains, and then assigning each of those domains a clock frequency. Two different approaches are illustrated, both based on the post-processing and analysis of the causation trace of a dataflow program. Methodology and initial experimental results are demonstrated in an at-size scenario using an MPEG-4 Simple Profile decoder implemented in a FPGA platform