64 research outputs found
Exploration of advanced CMOS technologies for new pixel detector concepts in High Energy Physics
This thesis presents the authorâs original concepts for the development of radiation hard monolithic pixel sensors that can replace hybrid pixel sensors in high energy physics experiments. It presents one of the first practical implementations of monolithic pixel sensors that potentially offer performance figures similar to those of the hybrid pixel technology with fewer material and for a fraction of the cost. Various pixel sensor prototypes in different technologies have been designed and manufactured for the first time. Prototypes allowed the characterization of the basic components of active pixel sensors and the evaluation of device parameters. Presented devices show strong indications that monolithic sensors can achieve very high radiation tolerance with parameters similar to the existing hybrid technology. Other application areas like X-ray imaging may also benefit from this development
A method for precise charge reconstruction with pixel detectors using binary hit information
A method is presented to precisely reconstruct charge spectra with pixel
detectors using binary hit information of individual pixels. The method is
independent of the charge information provided by the readout circuitry and has
a resolution mainly limited by the electronic noise. It relies on the ability
to change the detection threshold in small steps while counting hits from a
particle source. The errors are addressed and the performance of the method is
shown based on measurements with the ATLAS pixel chip FE-I4 bump bonded to a
230 {\mu}m 3D-silicon sensor. Charge spectra from radioactive sources and from
electron beams are presented serving as examples. It is demonstrated that a
charge resolution ({\sigma}<200 e) close to the electronic noise of the ATLAS
FE-I4 pixel chip can be achieved
Characterization and Verification Environment for the RD53A Pixel Readout Chip in 65 nm CMOS
The RD53 collaboration is currently designing a large scale prototype pixel
readout chip in 65 nm CMOS technology for the phase 2 upgrades at the HL-LHC.
The RD53A chip will be available by the end of the year 2017 and will be
extensively tested to confirm if the circuit and the architecture make a solid
foundation for the final pixel readout chips for the experiments at the HL-LHC.
A test and data acquisition system for the RD53A chip is currently under
development to perform single-chip and multi-chip module measurements. In
addition, the verification of the RD53A design is performed in a dedicated
simulation environment. The concept and the implementation of the test and data
acquisition system and the simulation environment, which are based on a modular
data acquisition and system testing framework, are presented in this work
Breakdown Performance of Guard Ring Designs for Pixel Detectors in CMOS Technology
Silicon pixel sensors manufactured using commercial CMOS processes are
promising instruments for high-energy particle physics experiments due to their
high yield and proven radiation hardness. As one of the essential factors for
the operation of detectors, the breakdown performance of pixel sensors
constitutes the upper limit of the operating voltage. Six types of passive CMOS
test structures were fabricated on high-resistivity wafers. Each of them
features a combination of different inter-pixel designs and sets of floating
guard rings, which differ from each other in the geometrical layout,
implantation type, and overhang structure. A comparative study based on leakage
current measurements in the sensor substrate of unirradiated samples was
carried out to identify correlations between guard ring designs and breakdown
voltages. TCAD simulations using the design parameters of the test structures
were performed to discuss the observations and, together with the measurements,
ultimately provide design features targeting higher breakdown voltages
Prototype Active Silicon Sensor in 150 nm HR-CMOS Technology for ATLAS Inner Detector Upgrade
The LHC Phase-II upgrade will lead to a significant increase in luminosity,
which in turn will bring new challenges for the operation of inner tracking
detectors. A possible solution is to use active silicon sensors, taking
advantage of commercial CMOS technologies. Currently ATLAS R&D programme is
qualifying a few commercial technologies in terms of suitability for this task.
In this paper a prototype designed in one of them (LFoundry 150 nm process)
will be discussed. The chip architecture will be described, including different
pixel types incorporated into the design, followed by simulation and
measurement results.Comment: 9 pages, 9 figures, TWEPP 2015 Conference, submitted to JINS
Neutron irradiation test of depleted CMOS pixel detector prototypes
Charge collection properties of depleted CMOS pixel detector prototypes
produced on p-type substrate of 2 kcm initial resistivity (by LFoundry
150 nm process) were studied using Edge-TCT method before and after neutron
irradiation. The test structures were produced for investigation of CMOS
technology in tracking detectors for experiments at HL-LHC upgrade.
Measurements were made with passive detector structures in which current pulses
induced on charge collecting electrodes could be directly observed. Thickness
of depleted layer was estimated and studied as function of neutron irradiation
fluence. An increase of depletion thickness was observed after first two
irradiation steps to 110 n/cm and 510
n/cm and attributed to initial acceptor removal. At higher fluences the
depletion thickness at given voltage decreases with increasing fluence because
of radiation induced defects contributing to the effective space charge
concentration. The behaviour is consistent with that of high resistivity
silicon used for standard particle detectors. The measured thickness of the
depleted layer after irradiation with 110 n/cm is more than
50 m at 100 V bias. This is sufficient to guarantee satisfactory
signal/noise performance on outer layers of pixel trackers in HL-LHC
experiments
BDAQ53, a versatile pixel detector readout and test system for the ATLAS and CMS HL-LHC upgrades
BDAQ53 is a readout system and verification framework for hybrid pixel
detector readout chips of the RD53 family. These chips are designed for the
upgrade of the inner tracking detectors of the ATLAS and CMS experiments.
BDAQ53 is used in applications where versatility and rapid customization are
required, such as in laboratory testing environments, test beam campaigns, and
permanent setups for quality control measurements. It consists of custom and
commercial hardware, a Python-based software framework, and FPGA firmware.
BDAQ53 is developed as open source software with both software and firmware
being hosted in a public repository.Comment: 6 pages, 6 figure
Charge collection and efficiency measurements of the TJ-Monopix2 DMAPS in 180nm CMOS technology
Monolithic CMOS pixel detectors have emerged as competitive contenders in the
field of high-energy particle physics detectors. By utilizing commercial
processes they offer high-volume production of such detectors. A series of
prototypes has been designed in a 180nm Tower process with depletion of the
sensor material and a column-drain readout architecture. The latest iteration,
TJ-Monopix2, features a large 2cm x 2cm matrix consisting of 512 x 512
pixels with 33.04um pitch. A small collection electrode design aims at low
power consumption and low noise while the radiation tolerance for high-energy
particle detector applications needs extra attention. With a goal to reach
radiation tolerance to levels of MeV ncm of
NIEL damage a modification of the standard process has been implemented by
adding a low-dosed n-type silicon implant across the pixel in order to allow
for homogeneous depletion of the sensor volume. Recent lab measurements and
beam tests were conducted for unirradiated modules to study electrical
characteristics and hit detection efficiency.Comment: Conference proceedings for PIXEL2022 conference, submitted to Po
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