Trigger processor for the APEX experiment at Argonne

An electron-positron spectrometer is being constructed at Argonne to search for correlated pairs emitted after heavy ion collisions. The trigger for this experiment requires the detection of a positron in either arm of the spectrometer. We describe the trigger for the experiment which selects events with positron annihilation radiation detected in an array of NaI crystals. 1 ref., 3 figs

Online Track Processor for the CDF Upgrade

A trigger track processor is being designed for the CDF upgrade. This processor identifies high momentum (PT \u3e 1.5 GeV/c) charged tracks in the new central outer tracking chamber for CDF 11. The track processor is called the extremely Fast Tracker (XFT). The XFT design is highly parallel to handle the input rate of 183 Gbits/sec and output rate of 44 Gbitslsec. The processor is pipelined and reports the results for a new event every 132 ns. The processor uses three stages, hit classification, segment finding, and segment linking. The pattern recognition algorithms for the three stages are implemented in programmable logic devices (PLDs) which allow for in-situ modification of the algorithm at any time. The PLDs reside on three different types of modules. Prototypes of each of these modules have been designed and built, and are presently undergoing testing. An overview of the track processor and results of testing are presented

System Architecture and Hardware Design of the CDF XFT Online Track Processor

A trigger track processor is being designed for CDF Run 2. This processor identifies high momentum (PT \u3e 1.5 GeV/c) charged tracks in the new central outer tracking chamber for the CDF I1 detector. The design of the track processor, called the extremely Fast Trackcr (XFT), is highly parallel and handle an input rate of 183 Gbitslsec and output rate of 44 Gbitdsec. The XFT is pipclined and reports the results for a new event every 132ns. The XFT uses threc stages, hit classification, segment finding, and segment linking. The pattem recognition algorithm for the three stages are implemented in Programmable Logic Devices (PLDs) which allow for in-situ modification of the algorithm at any time. Thc PLDs reside on three different types of modules. Prototypes of each of these modules have been designed and built, and are working. An overview of the hardware dcsign and the system architecture are prcsented