Constitutional Law: Evidence Obtained During an Administrative Search Without a Warrant Held Inadmissible in Subsequent Criminal Prosecution

For small integrated CMOS digital chips that communicate via analog signals the size and the cost of the AD-converters is a problem. An integrated CMOS AD-converter that could be built into the chip would solve this problem. In a CMOS process, the manufacturers only guarantee a very low accuracy of the recistances. The components of the ADC is therefore very inaccurate. The purpose of this report is to present a method for identication of the errors in the ADC and to perform simulations that evaluate the method. The estimated values can then be used in the chip to compensate for the errors in the ADC

Private-Law Models for Official Immunity

A method for correcting matching errors in an ADC is presented. The method uses the unknown input data from the application and does not require any test signal. Two algorithms for implementing the method are compared. One algorithm is general and works on any type of ADC. The other algorithm utilizes the subranged architecture of a specific ADC and is very simple to implement in hardware. The signal quality is similar for both algorithms

Construction Management and Design-Build/Fast Track Construction From the Perspective of a Generla Contractor

In the accompanying paper a method for blind (i.e., no calibration needed) estimation and compensation of the time errors in a time interleaved ADC system was presented. In this paper we evaluate this method. The Cramer-Rao bound is calculated, both for additive noise and random clock jitter. Monte-Carlo simulations have also been done to compare to the CRB. Finally, the estimation method is validated on measurements from areal time interleaved ADC system with 16 ADCs

Identification of AD converter

For small integrated CMOS digital chips that communicate via analog signals the size and the cost of the AD-converters is a problem. An integrated CMOS AD-converter that could be built into the chip would solve this problem. In a CMOS process, the manufacturers only guarantee a very low accuracy of the recistances. The components of the ADC is therefore very inaccurate. The purpose of this report is to present a method for identication of the errors in the ADC and to perform simulations that evaluate the method. The estimated values can then be used in the chip to compensate for the errors in the ADC

Blind Error Estimation and Correction in an AD Converter

For small integrated CMOS digital chips that communicate via analog signals the size and the cost of the AD-converters is a problem. An integrated CMOS AD-converter that could be built into the chip would solve this problem. In a CMOS process, the manufacturers only guarantee a very low accuracy of the recistances. The components of the ADC is therefore very inaccurate. The purpose of this report is to present a method for identification of the errors in the ADC and to perform simulations that evaluate the method. The algorithm should work while the ADC is used and it does not assume any knowledge of the input signal except that the distibution function is smooth. The estimated values can then be used in the chip to compensate for the errors in the ADC

Blind Equalization of Static Nonlinearities in SA-ADC

Due to imperfections in the manufacturing process of integrated A/D converters, there are static non-linear errors in the conversion from analog to digital signal. Calibration of these errors is time-consuming and expensive. In this paper a method for blind equlization of the errors is presented, i.e. the errors are estimated from the output signal only. The method has also been evaluated, with some modications, on measurements from a real A/D converter

Equalization of Time Errors in Time Interleaved ADC System - Part I: Theory

To significantly increase the sampling rate of an A/D converter (ADC), a time interleaved ADC system is a good option. The drawback of a time interleaved ADC system is that the ADCs are not exactly identical dueto errors in the manufacturing process. This means that time, gain and offset mismatch errors are introduced in the ADC system. These errors cause distortion in the sampled signal. In this paper we present a method for estimation and compensation of the time mismatch errors. The estimation method requires no knowledge about the input signal except that it should be band limited to the Nyquist frequency for the complete ADC system. This means that the errors can be estimated whilethe ADC is running. The method is also adaptive to slow changes in the time errors

Blind Estimation of Timing and Amplitude Offsets in Parallel A/D Converters

Parallel AD converter structures is one way to increase the sampling rate. Instead of increasing the sample rate in one AD converter, several AD converters with lower sampling rate can be used instead. A problem in these structures is that the time between samples is usually not equal because there are errors in the delays between the AD converters. There are also differences in the ground level in the different AD converters. We will here present a method to estimate the timing and amplitude offsets. The estimation algorithm works without any calibration signal, instead the usual input signal is used. The only assumption that is made about the signal is that most of the energy lies in a low frequency band. The AD converter structure will also be simulated to show that the method works