Nebulous hotspot and algorithm variability in computation lithography

Computation lithography relies on algorithms. However, these algorithms exhibit variability that can be as much as 5% (one standard deviation) of the critical dimension for the 65-nm technology. Using hotspot analysis and fixing as an example, we argue that such variability can be addressed on the algorithm level via controlling and eliminating its root causes, and on the application level by setting specifications that are commensurate with both the limitations of the algorithms and the goals of the application. © 2010 Society of Photo-Optical Instrumentation Engineers.published_or_final_versio

Computation lithography: Virtual reality and virtual virtuality

Computation lithography is enabled by a combination of physical understanding, mathematical abstraction, and implementation simplification. An application in the virtual world of computation lithography can be a virtual reality or a virtual virtuality depending on its engineering sensible-ness and technical feasibility. Examples under consideration include design-for- manufacturability and inverse lithography. © 2009 Optical Society of America.postprin

Regularization of inverse photomask synthesis to enhance manufacturability

Mask manufacturability has been considered as a major issue in the adoption of inverse lithography (IL) in practice. With smaller technology nodes, IL distorts the mask pattern more aggressively. The distorted mask often contains curvilinear contour and irregular shapes, which cast a heavy computation burden on segmentation and data preparation. Total variation (TV) has been used for regularization in previous work, but it is not very effective in regulating the mask shape to be rectangular. In this paper, we apply TV regularization not only on the mask image but also on the mask edges, which forces the curves of edges to be more vertical or horizontal, because they give smaller TV values. Except for rectilinearity, a group of geometrical specifications of the mask pattern set by mask manufacture rule control (MRC) is also important for mask manufacturability. To prevent these characteristics from appearing, we also propose an intervention scheme into the optimization framework. © 2009 Copyright SPIE - The International Society for Optical Engineering.published_or_final_versionThe SPIE Lithography Asia 2009, Taipei, Taiwan, 18 November 2009. in Proceedings of SPIE, 2009, v. 7520, p. 1-11, article no. 75200

Alternating phase-shifting mask design for low aberration sensitivity

Theories are developed to optimize the mask structure of alternating phase-shifting masks (PSMs) to minimize the average image placement error towards aberration under coherent imaging. The constraint of the optimization is a given mean value of RMS aberration, which corresponds to infinitely many sets of random Zernike coefficients. To begin the analysis, the image placement error is expressed as a function of the mask spectrum and the wave aberration. Monte Carlo analysis on the Zernike coefficients is then performed, which assures us that a global minimum of average image placement error is likely to occur at low phase widths. This result is confirmed by analytically considering the expected value of the square of the image placement error. By Golden Section Search, the optimal phase width is found to be 0.3707(λ/NA) at 0.07λ RMS aberration. This methodology of finding the optimal phase width is applicable to the design of all alternating PSMs.published_or_final_versio

A signomial programming approach for binary image restoration by penalized least squares

The authors present a novel optimization approach, using signomial programming (SP), to restore noise-corrupted binary and grayscale images. The approach requires the minimization of a penalized least squares functional over binary variables, which has led to the design of various approximation methods in the past. In this brief, we minimize the functional as a SP problem which is then converted into a reversed geometric programming (GP) problem and solved using standard GP solvers. Numerical experiments show that the proposed approach restores both degraded binary and grayscale images with good accuracy, and is over 20 times faster than the positive semidefinite programming approach. © 2007 IEEE.published_or_final_versio

Standard cell layout with regular contact placement

The practicability and methodology of applying regularly placed contacts on layout design of standard cells are studied. The regular placement enables more effective use of resolution enhancement technologies, which in turn allows for a reduction of critical dimensions. Although placing contacts on a grid adds restrictions during cell layout, overall circuit area can be made smaller by a careful selection of the grid pitch, allowing slight contact offset, applying double exposure, and shrinking the minimum size and pitch. The contact level of 250 nm standard cells was shrunk by 10%, resulting in an area change ranging from -20% to +25% with an average decrease of 5% for the 84 cells studied. The areas of two circuits, a finite-impulse-response (FIR) filter and an add-compare-select (ACS) unit in the Viterbi decoder, decrease by 4% and 2%, respectively.published_or_final_versio

New impulse (noncausality) test for descriptor systems by Mobius-transformation

Descriptor systems (DSs) are usually used to model very-large-scale integration (VLSI) circuit systems and multibody dynamics macromodeling. The analysis of DSs, however, is much more complicated than linear time-invariant (LTI) systems due to the poles at infinity. Mȯbius transformation (MT) provides a way to transform poles at infinity to finite poles and largely facilitates the reuse or adaptation of the standard techniques for LTI system to analyze DSs. Nonetheless, MT is well known in the literature and its potential use is currently less appreciated in the analysis of DSs. This paper gives a new way to the impulse (noncausality) test using the properties of the transformed LTI systems by MT. Moreover, the applications to the analysis of controllability, observability and regularity are given. Numerical examples are included to show the effectiveness of the proposed method. © 2012 Chinese Assoc of Automati.published_or_final_versio

Aberration-aware robust mask design with level-set-based inverse lithography

Optical proximity correction (OPC) is one of the most widely used Resolution Enhancement Techniques (RET) in mask designs. Conventional OPC is often designed for a set of nominal imaging parameters without giving sufficient attention to the process variations caused by aspherical wavefront leaving the exit pupil of the lithography system. As a result, the mask designed may deliver poor performance with process variations. In this paper, we first describe how a general point spread function (PSF) with wave aberration can degrade the output pattern quality, and then show how the wave aberration function can be incorporated into an inverse imaging framework for robust input mask pattern design against aberrations. A level-set-based time-dependent model can then be applied to solve it with appropriate finite difference schemes. The optimal mask gives more robust performance against either one specific type of aberration or a combination of different types of aberrations. © 2010 SPIE.published_or_final_versionThe Photomask and Next-Generation Lithography Mask Technology XVII, Yokohama, Japan, 13-14 April 2010. in Proceedings of SPIE, 2010, v. 7748, article no. 77481U, p. 1-

Performance optimization for gridded-layout standard cells

The grid placement of contacts and gates enables more effective use of resolution enhancement techniques, which in turn allow a reduction of critical dimensions. Although the regular placement adds restrictions during cell layout, the overall circuit area can be made smaller and the extra manufacturing cost can be kept to the lowest by a careful selection of the grid pitch, using template-trim lithography method, allowing random contact placement in the vertical direction, and using rectangular rather than square contacts. The purpose of this work is to optimize the gridded-layout-based process. The trade-off between the layout area and manufacturing cost, and the determination of the minimum grid pitch are discussed in this paper. We demonstrate that it is a 1-D scaling instead of the conventional 2-D scaling for standard cells and the narrow MOSFETs inside after the application of the gridded layout on the contact and gate levels. The corresponding effects on circuit performances, including the leakage current, are also explored.published_or_final_versio

Standard cell design with resolution-enhancement-technique-driven regularly placed contacts and gates

The practicability and methodology of applying resolution-enhancement- technique-driven regularly placed contacts and gates on standard cell layout design are studied. The regular placement enables more effective use of resolution enhancement techniques (RETs), which in turn enables a reduction of critical dimensions. Although regular placement of contacts and gates adds restrictions during cell layout, the over-all circuit area can be made smaller and the number of extra masks and exposures can be kept to the lowest by careful selection of the grid pitch, using template-trim chromeless phase-shifting lithography approaches, enabling unrestricted contact placement in one direction, and using rectangular rather than square contacts. Four different fabrication-friendly layouts are compared. The average area change of 64 standard cells in a 130-nm library range from -4.2 to -15.8% with the four fabricationfriendly layout approaches. The area change of five test circuits using the four approaches range from -16.2 to +2.6%. Dynamic power consumption and intrinsic delay also improve with the decrease in circuits area, which is verified with the examination results. © 2005 Society of Pnoto-Optical Instrumentation Engineers.published_or_final_versio