A community small-scale wind generation project in Peru

Electrification systems based on renewable energy have proven to be suitable for providing decentralized electricity to isolated communities. Electricity generated through wind power is one of the technical options available, although infrequently used to date. This article aims to describe the main aspects of technical design, implementation and management of the first small-scale community wind generation project for rural electrification in Peru. This project took place in the community of El Alumbre, in the region of Cajamarca, which is a mountainous area characterized by low to medium wind speeds. This project, implemented by Soluciones Prácticas – Practical Action (Peru), brought electric power to the 33 households (a total of 150 inhabitants) as well as the school and health center of the community.Peer ReviewedPostprint (published version

Switched-capacitor neural networks for linear programming

A circuit for online solving of linear programming problems is presented. The circuit uses switched-capacitor techniques and is thus suitable for monolithic implementation. The connection of the proposed circuit to analogue neural networks is also outlined.Comisión Interministerial de Ciencia y Tecnología ME87-000

Analog integrated neural-like circuits for nonlinear programming

A systematic approach for the design of analog neural nonlinear programming solvers using switched-capacitor (SC) integrated circuit techniques is presented. The method is based on formulating a dynamic gradient system whose state evolves in time towards the solution point of the corresponding programming problem. A neuron cell for the linear and the quadratic problem suitable for monolithic implementation is introduced. The design of this neuron and its corresponding synapses using SC techniques is considered in detail. An SC circuit architecture based on a reduced set of basic building blocks with high modularity is presented. Simulation results using a mixed-mode simulator (DIANA) and experimental results from breadboard prototypes are included, illustrating the validity of the proposed technique

Analog Neural Programmable Optimizers in CMOS VLSI Technologies

A 3-μm CMOS IC is presented demonstrating the concept of an analog neural system for constrained optimization. A serial time-multiplexed general-purpose architecture is introduced for the real-time solution of this kind of problem in MOS VLSI. This architecture is a fully programmable and reconfigurable one exploiting SC techniques for the analog part and making extensive use of digital techniques for programmability

Current-Mode Techniques for the Implementation of Continuous- and Discrete-Time Cellular Neural Networks

This paper presents a unified, comprehensive approach to the design of continuous-time (CT) and discrete-time (DT) cellular neural networks (CNN) using CMOS current-mode analog techniques. The net input signals are currents instead of voltages as presented in previous approaches, thus avoiding the need for current-to-voltage dedicated interfaces in image processing tasks with photosensor devices. Outputs may be either currents or voltages. Cell design relies on exploitation of current mirror properties for the efficient implementation of both linear and nonlinear analog operators. These cells are simpler and easier to design than those found in previously reported CT and DT-CNN devices. Basic design issues are covered, together with discussions on the influence of nonidealities and advanced circuit design issues as well as design for manufacturability considerations associated with statistical analysis. Three prototypes have been designed for l.6-pm n-well CMOS technologies. One is discrete-time and can be reconfigured via local logic for noise removal, feature extraction (borders and edges), shadow detection, hole filling, and connected component detection (CCD) on a rectangular grid with unity neighborhood radius. The other two prototypes are continuous-time and fixed template: one for CCD and other for noise removal. Experimental results are given illustrating performance of these prototypes

Cross-cultural factors in international branding

This is the second special issue resulting from the symposium titled ‘The Brand and Its History’. This issue aims at deepening the knowledge of the historical and cultural roots of the origin, uses, and meanings of modern branding. This editorial summarises previous contributions from economic, marketing, and historical literature; presents the main findings of the seven articles included in this issue; and reflects on possible further researc

Trademarks in branding: Legal issues and commercial practices

This article was originally published with error, which have now been corrected in the online and print versions. Please see Correction (http://dx.doi.org/10.1080/00076791.2019.1568704)The call for a special symposium on ‘The Brand and Its History’ has led to two journal issues that focus on trademarks and brands, respectively. This issue is devoted to trademarks, the more concrete, well-documented, and measurable aspect of brands. This editorial introduces trademark studies; summarises previous contributions from economic, legal, business, and historical literature; provides a short overview of the topics and findings of the seven articles included in this issue; and reflects on further researc

Analog neural networks for real-time constrained optimization

Architectures and circuit techniques for implementing general piecewise constrained optimization problems using VLSI techniques are explored. Discrete-time analog techniques are considered due to their inherent accuracy, programmability, and reconfigurability. A general architecture for minimizing piecewise functions by using gradient schemes is introduced. Switched-capacitor (SC) building blocks featuring improved characteristics in terms of area occupation and operation speed are presented. The implementation of the architectures by using the newest switched-current techniques is discussed. The layout of a 3-μm CMOS SC prototype for a quadratic optimization problem with linear constraints is given

A Model for VLSI implementation of CNN image processing chips using current-mode techniques

A new Cellular Neural Network model is proposed which allows simpler and faster VLSI implementation than previous models. Current-mode building blocks are presented for the design of CMOS image preprocessing chips (feature extraction, noise filtering , compound component detection, etc.) using the cellular neural network paradigm. Area evaluation for the new model shows a reduction off about 50% as compared to the use of current-mode techniques with conventional models. Experimental measurements of CMOS prototypes designed in a 1.6 μm n-well double-metal single-poly technology are reported