Low Temperature Characterization and Modeling of FDSOI Transistors for Cryo CMOS Applications

The wide range of cryogenic applications, such as spatial, high performance computing or high-energy physics, has boosted the investigation of CMOS technology performance down to cryogenic temperatures. In particular, the readout electronics of quantum computers operating at low temperature requires larger bandwidth than spatial applications, so that advanced CMOS node has to be considered. FDSOI technology appears as a valuable solution for co-integration between qubits and consistent engineering of control and read-out. However, there is still lack of reports on literature concerning advanced CMOS nodes behavior at deep cryogenic operation, from devices electrostatics to mismatch and self-heating, all requested for the development of robust design tools. For these reasons, this chapter presents a review of electrical characterization and modeling results recently obtained on ultra-thin film FDSOI MOSFETs down to 4.2 K

Contact resistances in trigate and FinFET devices in a Non-Equilibrium Green's Functions approach

We compute the contact resistances $R_{\rm c}$ in trigate and FinFET devices with widths and heights in the 4 to 24 nm range using a Non-Equilibrium Green's Functions approach. Electron-phonon, surface roughness and Coulomb scattering are taken into account. We show that $R_{\rm c}$ represents a significant part of the total resistance of devices with sub-30 nm gate lengths. The analysis of the quasi-Fermi level profile reveals that the spacers between the heavily doped source/drain and the gate are major contributors to the contact resistance. The conductance is indeed limited by the poor electrostatic control over the carrier density under the spacers. We then disentangle the ballistic and diffusive components of $R_{\rm c}$, and analyze the impact of different design parameters (cross section and doping profile in the contacts) on the electrical performances of the devices. The contact resistance and variability rapidly increase when the cross sectional area of the channel goes below $\simeq 50$ nm$^2$. We also highlight the role of the charges trapped at the interface between silicon and the spacer material.Comment: 16 pages, 15 figure

Caractérisation Électrique et Modélisation du Transport dans les Dispositifs CMOS Avancés

La micro-électronique est considérée comme une technologie révolutionnaire compte-tenu de la dynamique qu'elle a insufflée à l'économie mondiale depuis l'invention du circuit intégré dans les années 50. Jusqu'à récemment, les défis technologiques relevés ont consisté à conserver une ligne directrice de développement fondée sur une simple réduction des dimensions du transistor MOS, faisant basculer la micro-électronique dans l'ère de la nanoélectronique. Industriels et chercheurs tentent aujourd'hui de repousser les limites physiques imposées par la réduction d'échelle en agissant sur différents leviers technologiques, afin d'améliorer les performances des dispositifs sans avoir à en réduire les dimensions. Les travaux présentés résument mon activité de recherche menée au CEA-Léti depuis 2001, dans le contexte général du développement des technologies CMOS pour les noeuds avancés (i.e. le 65nm pour le début des années 2000, le 14nm et en deçà à l'heure actuelle), avec un focus plus particuliers sur l'étude du transport dans le canal des transistors MOS. Trois voies principales ont été explorées, et seront analysées et commentées : * les nouveaux matériaux de grille, avec l'introduction des oxydes à forte permittivité (high-κ) et des grilles métalliques. * l'ingénierie de la mobilité, avec entre autres l'utilisation de matériaux à plus forte mobilité comme les alliages SiGe, ou encore l'exploitation des contraintes. * les nouvelles architectures de transistor, avec la réalisation de films minces et de transistors multi-grilles ou à grille enrobante

Etude du transport électronique dans des systèmes mésoscopiques : interféromètre à anneau

The present work deals with the study of transport properties of an interferential system, fabricated at the interface of a modulation doped AlGaAs/GaAs semiconductor heterostructure. The principle of this electron interferometer is based on the solid state Aharonov-Bohm effect. This effect is due to the influence of an electromagnetic field on the phase of the electron wave function. We have measured high mobility samples, in which the phase coherence length Lphi is greater than the dimensions of the system, in the ballistic transport regime. First, we investigate the temperature dependence of AB oscillations. We show that the results can be understood in terms of transmission probability through the eigenstates of the ring. A numerical model based on weak coupling between the ring and the leads fits the experimental data, provided that we take into account the charging energy due to Coulomb repulsions. Other experimental results strengthen this assumption of weak coupling. When the gate voltage, which cover the entire structure, i.e both arms, is swept in a continuous way, the phase of the oscillations of magnetoresistance switches between 0 and pi. These changes are accompanied by intermediate h/2e oscillations. Similar effects are observed when a DC-bias current is applied. These measurements suggest that the electronic properties of the ring are directly connected to the energy spectrum, so that we have performed a spectroscopic investigation of a mesoscopic ring.Ce travail s'intéresse à l'étude des propriétés de transport d'un système interférentiel fabriqué à l'interface d'une hétérostructure semiconductrice AlGaAs/GaAs à modulation de dopage. Il s'agit d'un interféromètre électronique en forme d'anneau, dont le principe de base repose sur l'effet Aharonov-Bohm (AB), transposé à la physique du solide. Cet effet est directement dû à l'influence d'un champ électromagnétique sur la phase de la fonction d'onde d'un électron. Nos mesures ont été réalisées sur des échantillons à forte mobilité, pour lesquels la longueur de cohérence de phase Lphi est grande devant les dimensions du système, et dans le régime de transport balistique. Tout d'abord, notre étude expérimentale a porté sur la dépendance en température des oscillations AB. Nous avons montré que celle-ci peut être comprise en termes de probabilité de transmission à travers les états propres de l'anneau. Un modèle numérique basé dur le faible couplage entre l'anneau et les réservoirs d'électrons permet de retrouver les données expérimentales, à condition toutefois de tenir compte de l'énergie de charge due aux répulsions Coulombiennes. Les résultats expérimentaux suivants renforcent encore cette hypothèse, en s'inscrivant dans la cohérence du raisonnement. Ainsi, lorsque la tension de grille, qui recouvre la totalité de la structure, à savoir les deux bras de l'anneau, varie de manière continue, la phase des oscillations de la magnétorésistance change brusquement de 0 à pi, avec l'apparition d'oscillations intermédiaires de fréquence double, c'est à dire de période apparente h/2e. Les mêmes effets sont observés lorsque l'on applique un courant de polarisation. Ces mesures suggèrent que les propriétés électroniques de l'anneau sont le reflet direct du spectre, et que nous avons donc réalisé la spectroscopie d'un anneau mésoscopique

On the modelling of temperature dependence of subthreshold swing in MOSFETs down to cryogenic temperature

International audienc

Cryogenic electronics for quantum computing ICs: what can bring FDSOI

International audienceWe present an overview of the performances of FDSOI CMOS transistors down to deep cryogenic temperature, highlighting in particular the benefits brought by the back bias. FDSOI transistors are operational from room temperature down to temperature as lowas 100mK. The main DC electrical characteristics, as well as variability properties and reliability are measured and analyzed.We also point out specific behaviors appearing at cryogenic temperature, and discuss their physical origin and modeling

Cryogenic electronics for quantum computing ICs: what can bring FDSOI

International audienceWe present an overview of the performances of FDSOI CMOS transistors down to deep cryogenic temperature, highlighting in particular the benefits brought by the back bias. FDSOI transistors are operational from room temperature down to temperature as lowas 100mK. The main DC electrical characteristics, as well as variability properties and reliability are measured and analyzed.We also point out specific behaviors appearing at cryogenic temperature, and discuss their physical origin and modeling

Piezoresistivity in unstrained and strained SOI MOSFETs

session: FDSOIInternational audienceWe hereby present the extraction and the study of piezoresistive (PR) coefficients in MOSFETs built on unstrained and strained SOI substrates. We have evidenced a strong dependence of these PR with the inversion charge density in particular for PMOS. These results are well explained by the Si bandstructure calculation which enlightens the effect of the strain and of the electric confinement on carrier mobility, up to high tensile strain values

New method for individual electrical characterization of stacked SOI nanowire MOSFETs

International audienceA new systematic procedure to separate the electrical characteristics of advanced stacked nanowires (NWs) with emphasis on mobility extraction is presented. The proposed method is based on I-V measurements varying the back gate bias (VB) and consists of three basic main steps, accounting for VB influence on transport parameters. Lower mobility was obtained for the top GAA NW in comparison to bottom -NW. Temperature dependence of carrier mobility is also studied through the proposed method up to 150°C

Characterization and role of deep traps on the radio frequency performances of high resistivity substrates

In this study, high-resistivity gold-implanted silicon substrates developed for radio frequency (RF) applications were characterized. By varying PICTS (Photo-Induced Current Transient Spectroscopy) measurement conditions such as the illumination wavelength, we identified the signature and the nature of four dominant traps. Two were electron traps and the others were hole traps. All of the related defects involved gold atoms. RF simulations of coplanar waveguide transmission lines integrated on these substrates were carried out, based on the trap properties extracted from PICTS results. A good agreement between RF experimental data and simulations was achieved by tuning the trap concentrations. Finally, the gold density extracted from the fit was successfully compared with the secondary ion mass spectrometry profile and an explanation of the role of the traps in RF behavior of the substrate was given