Effect of mask discretization on performance of silicon arrayed waveguide gratings

We studied the impact of the lithography mask discretization on silicon arrayed waveguide grating (AWG) performance. When we decreased the mask grid from 5 to 1 nm, we observed an experimental improvement in crosstalk of 2.7-6 dB and cumulative crosstalk improvement of 1.2-5 dB, depending on the wavelength channel spacing and the number of output channels. We demonstrate the effect for the AWGs with 200-and 400-GHz channel spacing, with 4, 8, and 16 output wavelength channels. With 1-nm mask grid, the average crosstalk is -26 and -23 dB for 400- and 200-GHz devices, respectively. This is the lowest crosstalk for silicon AWGs reported to the best of our knowledge. A simulation study is performed by looking specifically at phase errors due to mask grid snapping (ignoring other phase error sources), which shows an expected improvement in crosstalk of 12 dB

Low-power, 10-Gbps 1.5-Vpp differential CMOS driver for a silicon electro-optic ring modulator

We present a novel driver circuit enabling electro-optic modulation with high extinction ratio from a co-designed silicon ring modulator. The driver circuit provides an asymmetric differential output at 10Gbps with a voltage swing up to 1.5V(pp) from a single 1.0V supply, maximizing the resonance-wavelength shift of depletion-type ring modulators while avoiding carrier injection. A test chip containing 4 reconfigurable driver circuits was fabricated in 40nm CMOS technology. The measured energy consumption for driving a 100fF capacitive load at 10Gbps was as low as 125fJ/bit and 220fJ/bit at 1V(pp) and 1.5V(pp) respectively. After flip-chip integration with ring modulators on a silicon-photonics chip, the power consumption was measured to be 210fJ/bit and 350fJ/bit respectively

Co-integration of Ge detectors and Si modulators in an advanced Si photonics platform

A Si photonics platform is described, co-integrating advanced passive components with Si modulators and Ge detectors. This platform is developed on a 200mm CMOS toolset, compatible with a 130nm CMOS baseline. The paper describes the process flow, and describes the performance of selected electro-optical devices to demonstrate the viability of the flow

Record low-loss hybrid rib/wire waveguides for silicon photonic circuits

We report a very low-loss hybrid silicon waveguide circuit consisting of straight rib sections with a propagation loss of 0.272±0.012 dB/cm and compact photonic wire bends of 5µm radius with a loss of 0.0273±0.0004 dB/90° bend

SOI thickness uniformity improvement using corrective etching for silicon nano-photonic device

We present our recent results on Si thickness uniformity improvement in a SOI wafer. We improved the thickness uniformity by 50%. The effect of the correction process on the propagation loss and device uniformity is also presented

Detection or modulation at 35 Gbit/s with a standard CMOS-processed optical waveguide

Light modulation and detection within a single SOI waveguide is demonstrated at 1550 nm. Multi-functional devices allow simplified transceiver systems. Savings in the number of fabrication steps increase the yield and reduce costs