Electrocardiogram on Wireless Sensor Nodes

Wireless sensor nodes are applicable in a wide range of situations such as the medical, industrial or environmental domains, but the focus is on the biomedical domain. This paper presents the steps taken to develop a low power processor using Silicon Hive technology and mapping an electrocardiogram analysis algorithm on that processor. Today\u27s energy-scavengers are able to deliver 100microwatt. This is the global power constraint of the sensor node. With a total power consumption of 16microwatt, the DSP processes the samples, compresses them into extracted parameters and the results are sent out by means of a radio

Low-Power Reconfigurable Architectures for High-Performance Mobile Nodes

Modern embedded systems have an emerging demand on high performance and low power circuits. Traditionally special functional units for each application are developed separately. These are plugged to a general purpose processors to extend its instruction set making it an application specific instruction set processor. As this strategy reaches its boundaries in area and complexity reconfigurable architectures propose to be more flexible. Thus combining both approaches to a reconfigurable application specific processor is going to be the upcoming solution for future embedded systems

SystemC Model of Power Side-Channel Attacks Against AI Accelerators: Superstition or not?

As training artificial intelligence (AI) models is a lengthy and hence costly process, leakage of such a model's internal parameters is highly undesirable. In the case of AI accelerators, side-channel information leakage opens up the threat scenario of extracting the internal secrets of pre-trained models. Therefore, sufficiently elaborate methods for design verification as well as fault and security evaluation at the electronic system level are in demand. In this paper, we propose estimating information leakage from the early design steps of AI accelerators to aid in a more robust architectural design. We first introduce the threat scenario before diving into SystemC as a standard method for early design evaluation and how this can be applied to threat modeling. We present two successful side-channel attack methods executed via SystemC-based power modeling: correlation power analysis and template attack, both leading to total information leakage. The presented models are verified against an industry-standard netlist-level power estimation to prove general feasibility and determine accuracy. Consequently, we explore the impact of additive noise in our simulation to establish indicators for early threat evaluation. The presented approach is again validated via a model-vs-netlist comparison, showing high accuracy of the achieved results. This work hence is a solid step towards fast attack deployment and, subsequently, the design of attack-resilient AI accelerators

A comparative survey of open-source application-class RISC-V processor implementations

Revision notice: This version does not contain CVA6 SPEC CPU2017 scores. There is an updated version available with additional CVA6 SPEC CPU2017 scores: https://doi.org/10.24355/dbbs.084-202105101615-

A comparative survey of open-source application-class RISC-V processor implementations

The numerous emerging implementations of RISC-V processors and frameworks underline the success of this Instruction Set Architecture (ISA) specification. The free and open source character of many implementations facilitates their adoption in academic and commercial projects. As yet it is not easy to say which implementation fits best for a system with given requirements such as processing performance or power consumption. With varying backgrounds and histories, the developed RISC-V processors are very different from each other. Comparisons are difficult, because results are reported for arbitrary technologies and configuration settings. Scaling factors are used to draw comparisons, but this gives only rough estimates. In order to give more substantiated results, this paper compares the most prominent open-source application-class RISC-V projects by running identical benchmarks on identical platforms with defined configuration settings. The Rocket, BOOM, CVA6, and SHAKTI C-Class implementations are evaluated for processing performance, area and resource utilization, power consumption as well as efficiency. Results are presented for the Xilinx Virtex UltraScale+ family and GlobalFoundries 22FDX ASIC technology

Energy efficient cooperative spectrum sensing in Cognitive Radio Sensor Network Using FPGA: A survey

Cognitive Radio Sensor Network (CRSN) is a network of deployed wireless sensor nodes integrated with Cognitive Radio (CR) capability. It is a most promising technology to resolve spectrum scarcity resources, coexistence with another network in ISM band, and prolonging the lifetime in Wireless Sensor Networks (WSN). One of the major challenges in CRSN is the energy consumption due to the inherited limited energy from its traditional WSN. Cooperative Spectrum Sensing (CSS) is utilized used to improve the sensing performance in multipath fading, shadowing and receiver uncertainty. In this paper, we present the basic difference between the conventional WSN and the CRSN, a comprehensive overview of non-cooperative spectrum sensing methods and state-of-the-art research of EE in CRSN. Furthermore, we introduce the most commonly utilized platforms and the appropriate tools in CR field