Implantation du décodeur entropique de JPEG 2000 basée sur la reconfiguration dynamique des FPGAs

Cet article a pour objet la mise en oeuvre de la reconfiguration dynamique des FPGAs. L'application envisagée ici, est le décodeur entropique de JPEG 2000 et la procédure MQ-Décode. Des critères d'analyse pour les différentes implantations seront tout d'abord définis, puis nous présenterons la norme JPEG 2000 et l'architecture employée

Simulation de séquences d'images haute résolution dégradées par la turbulence atmosphérique

Nous présentons une méthode originale de simulation d'images haute résolution dégradées par la turbulence atmosphérique. Ces images peuvent être simulées aussi bien dans le cas de fort anisoplanétisme qu'en isoplanétisme. En outre, nous prenons en compte l'aspect temporel de l'évolution de la turbulence dans le but de construire une séquence d'images dégradées prises à une fréquence d'échantillonnage donnée

Traitement des signaux et images en temps réel ("implantation de H.264 sur MPSoC")

Cette thèse est élaborée en cotutelle entre l université Badji Mokhtar (Laboratoire LERICA) et l université de bourgogne (Laboratoire LE2I, UMR CNRS 5158). Elle constitue une contribution à l étude et l implantation de l encodeur H.264/AVC. Durent l évolution des normes de compression vidéo, une réalité sure est vérifiée de plus en plus : avoir une bonne performance du processus de compression nécessite l élaboration d équipements beaucoup plus performants en termes de puissance de calcul, de flexibilité et de portabilité et ceci afin de répondre aux exigences des différents traitements et satisfaire au critère Temps Réel . Pour assurer un temps réel pour ce genre d applications, une solution reste possible est l utilisation des systèmes sur puce (SoC) ou bien des systèmes multiprocesseurs sur puce (MPSoC) implantés sur des plateformes reconfigurables à base de circuit FPGA. L objective de cette thèse consiste à l étude et l implantation des algorithmes de traitement des signaux et images et en particulier la norme H.264/AVC, et cela dans le but d assurer un temps réel pour le cycle codage-décodage. Nous utilisons deux plateformes FPGA de Xilinx (ML501 et XUPV5). Dans la littérature, il existe déjà plusieurs implémentations du décodeur. Pour l encodeur, malgré les efforts énormes réalisés, il reste toujours du travail pour l optimisation des algorithmes et l extraction des parallélismes possibles surtout avec une variété de profils et de niveaux de la norme H.264/AVC.Dans un premier temps de cette thèse, nous proposons une implantation matérielle d un contrôleur mémoire spécialement pour l encodeur H.264/AVC. Ce contrôleur est réalisé en ajoutant, au contrôleur mémoire DDR2 des deux plateformes de Xilinx, une couche intelligente capable de calculer les adresses et récupérer les données nécessaires pour les différents modules de traitement de l encodeur. Ensuite, nous proposons des implantations matérielles (niveau RTL) des modules de traitement de l encodeur H.264. Sur ces implantations, nous allons exploiter les deux principes de parallélisme et de pipelining autorisé par l encodeur en vue de la grande dépendance inter-blocs. Nous avons ainsi proposé plusieurs améliorations et nouvelles techniques dans les modules de la chaine Intra et le filtre anti-blocs. A la fin de cette thèse, nous utilisons les modules réalisés en matériels pour la l implantation Matérielle/logicielle de l encodeur H.264/AVC. Des résultats de synthèse et de simulation, en utilisant les deux plateformes de Xilinx, sont montrés et comparés avec les autres implémentations existantesThis thesis has been carried out in joint supervision between the Badji Mokhtar University (LERICA Laboratory) and the University of Burgundy (LE2I laboratory, UMR CNRS 5158). It is a contribution to the study and implementation of the H.264/AVC encoder. The evolution in video coding standards have historically demanded stringent performances of the compression process, which imposes the development of platforms that perform much better in terms of computing power, flexibility and portability. Such demands are necessary to fulfill requirements of the different treatments and to meet "Real Time" processing constraints. In order to ensure real-time performances, a possible solution is to made use of systems on chip (SoC) or multiprocessor systems on chip (MPSoC) built on platforms based reconfigurable FPGAs. The objective of this thesis is the study and implementation of algorithms for signal and image processing (in particular the H.264/AVC standard); especial attention was given to provide real-time coding-decoding cycles. We use two FPGA platforms (ML501 and XUPV5 from Xilinx) to implement our architectures. In the literature, there are already several implementations of the decoder. For the encoder part, despite the enormous efforts made, work remains to optimize algorithms and extract the inherent parallelism of the architecture. This is especially true with a variety of profiles and levels of H.264/AVC. Initially, we proposed a hardware implementation of a memory controller specifically targeted to the H.264/AVC encoder. This controller is obtained by adding, to the DDR2 memory controller, an intelligent layer capable of calculating the addresses and to retrieve the necessary data for several of the processing modules of the encoder. Afterwards, we proposed hardware implementations (RTL) for the processing modules of the H.264 encoder. In these implementations, we made use of principles of parallelism and pipelining, taking into account the constraints imposed by the inter-block dependency in the encoder. We proposed several enhancements and new technologies in the channel Intra modules and the deblocking filter. At the end of this thesis, we use the modules implemented in hardware for implementing the H.264/AVC encoder in a hardware/software design. Synthesis and simulation results, using both platforms for Xilinx, are shown and compared with other existing implementationsDIJON-BU Doc.électronique (212319901) / SudocSudocFranceF

Combining Haar Wavelet and Karhunen Loeve Transforms for Medical Images Watermarking

International audienceThis paper presents a novel watermarking method, applied to the medical imaging domain, used to embed the patient's data into the corresponding image or set of images used for the diagnosis. The main objective behind the proposed technique is to perform the watermarking of the medical images in such a way that the three main attributes of the hidden information (i.e. imperceptibility, robustness, and integration rate) can be jointly ameliorated as much as possible. These attributes determine the effectiveness of the watermark, resistance to external attacks and increase the integration rate. In order to improve the robustness, a combination of the characteristics of Discrete Wavelet and Karhunen Loeve Transforms is proposed. The Karhunen Loeve Transform is applied on the sub-blocks (sized 8x8) of the different wavelet coefficients (in the HL2, LH2 and HH2 subbands). In this manner, the watermark will be adapted according to the energy values of each of the Karhunen Loeve components, with the aim of ensuring a better watermark extraction under various types of attacks. For the correct identification of inserted data, the use of an Errors Correcting Code (ECC) mechanism is required for the check and, if possible, the correction of errors introduced into the inserted data. Concerning the enhancement of the imperceptibility factor, the main goal is to determine the optimal value of the visibility factor, which depends on several parameters of the DWT and the KLT transforms. As a first step, a Fuzzy Inference System (FIS) has been set up and then applied to determine an initial visibility factor value. Several features extracted from the Co-Occurrence matrix are used as an input to the FIS and used to determine an initial visibility factor for each block; these values are subsequently re-weighted in function of the eigenvalues extracted from each sub-block. Regarding the integration rate, the previous works insert one bit per coefficient. In our proposal, the integration of the data to be hidden is 3 bits per coefficient so that we increase the integration rate by a factor of magnitude 3

A High-level Methodology for Automatically Generating Dynamic Partially Reconfigurable Systems using IP-XACT and the UML MARTE Profile

International audienceDynamic Partial Reconfiguration (DPR) has been introduced in recent years as a method to increase the flexibility of FPGA designs. However, using DPR for building com- plex systems remains a daunting task. Recently, approaches based on Model-Driven Engi- neering (MDE) and UML MARTE standard have emerged which aim to simplify the design of complex SoCs, and in some cases, DPR systems. Nevertheless, many of these approaches lacked a standard intermediate representation to pass from high-levels of descriptions to ex- ecutable models. However, with the recent standardization of the IP-XACT specification, there is an increasing interest to use it in MDE methodologies to ease system integration and to enable design flow automation. In this paper we propose an MARTE/MDE approach which exploits the capabilities of IP-XACT to model and automatically generate DPR SoC designs. We present the MARTE modeling concepts and how these models are mapped to IP-XACT objects; the emphasis is given to the generation of IP cores that can be used in the Xilinx EDK (Embedded Design Kit) environment, since we aim to develop a complete flow around their Dynamic Partial Reconfiguration design flow. Finally, we present a case study integrating the presented concepts, showing the benefits in design efforts compared with a purely VHDL approach and using solely EDK. Experimental results show a reduction of the design efforts required to obtain the netlist required for the DPR design flow from hours required in VHDL and Xilinx EDK, to less the one hour and minutes for IP integration

MEMORY REQUIREMENTS FOR HARDWARE IMPLEMENTATION OF THE H.264 ENCODER MODULES

For a hardware implementation of any image processing algorithm, it is necessary to study the input/output of each processing module  even  before  studying  the  internal  architecture  of  these modules. And  that  to  prepare  a  simulation  platform, with internal and external memory, necessary  to  load and  to prepare  the  input  for  the modules. These memories are also used as intermediate  component  between  the  different modules  to  provide  the  possibility  of  parallelism.  In  this work we  give  the architecture  of  internal  and  external  memory  used  by  the  H.264  encoder  in  order  to  develop  a  simulation  platform  for processing modules. This platform can be realized in FPGA platform chosen according to the memory requirements

Facilitating IP deployment in a MARTE-based MDE methodology using IP-XACT: a XILINX EDK case study

International audienceIn this paper we present framework for the deployment of hardware IPs at high-levels of abstraction. It is based in a model- driven approach that aims at the automatic generation of Dynamic Partial Reconfiguration designs created in Xilinx Platform Studio (XPS). Contrary to previous approaches, we make use of the IP-XACT standard to facilitate the deployment of hardware IPs, their parameterization and subsequent integration. We propose an extension to the MARTE profile for IP deployment, and we introduce the necessary model transformations to obtain a high- level representation from an IP-XACT component library. These models are then used to create a platform in MARTE that abstracts the technologic aspects of the chosen back-end. The so- obtained UML platform is transformed in an IP-XACT design, which is exploited to generate the files used by XPS for system implementation. In this way, we promote IP reuse and deployment while remaining back-end independent, by using specific vendor extensions. Finally, we analyze the advantages of the proposed methodology by a case study in system integration

Contribution à la mise en œuvre d une plate-forme de prototypage rapide pour la conception des systèmes sur puce

DIJON-BU Sciences Economie (212312102) / SudocSudocFranceF

A HARDWARE SOLUTION FOR HEVC INTRA PREDICTION LOSSLESS CODING

International audienceThe lossless coding mode of the High Efficiency Video Coding (HEVC) main profile that bypasses transform, quantization, and in-loop filters is described. Compared to the HEVC non-lossless coding mode, the HEVC lossless coding mode provides perfect fidelity and an average bit-rate reduction of 3.2%–13.2%. It also significantly outperforms the existing lossless compression solutions, such as JPEG2000 and JPEG-LS for images as well as WinRAR for data archiving. A fully parallel-based solution is presented in this paper in order to reduce processing time and computation complexity resulting from intra prediction. Two higher performance structures are designed to perform angular and planar modes, and implemented in five engines which compose our architecture. This solution supports all intra prediction modes for all prediction unit sizes. The synthesis results show that our design can run at 256 MHz for FPGA Xilinx Virtex 7 and is capable to process real time 120 1080p frames per second

An Efficient Hardware Architecture for the HEVC Intra Prediction

International audienceA novel intra prediction hardware architecture forthe High Efficiency Video Coding (HEVC) is presented in thispaper in order to reduce the computation complexity within thisstandard and to accelerate the concerned calculations, and thusto process more and more of video frames at high resolutions. Wepropose a new pipelined structure that we called ProcessingElement (PE) to calculate the angular prediction modes, and werepeat it in three paths that our design composed of. And wepresent, in this paper, a dynamic structure to carry out thePlanar mode. This architecture supports all intra predictionmodes for 8x8 and 4x4 prediction unit sizes. The synthesis resultsshow that our proposition can operate at 225 MHz for XilinxVirtex 6 FPGA and is capable to process real time 120 frames persecond for 1080p video sequences or to process real time 30frames per second for 4K video sequences