Electrical characterization of N-MOS and P-MOS Junctionless Gate-All-Around (GAA) MOSFET for an inverter application

This paper presents a numerical simulation to examine the electrical performance of a Junctionless Gate-All-Around (JGAA) Field Effect Transistor (FET) as an inverter. The advantages of the device offer smaller threshold voltage, lower leakage current, better electrostatic control, better device performance and can operate at a high speed. Thus, to examine the potential of the device for an inverter application, the characterization of the Junctionless GAA MOSFET is performed to identify the critical device parameters in optimizing the device performance. Besides, the optimization of the device is aimed to be used to meet IRDS standard, particularly for a low power application. The characterization of electrical properties conducted based on carrier concentration, radius, gate length and drain voltage. It is found that the drain voltage and gate length give a significant impact on the threshold voltage and on-state current of the Junctionless GAA MOSFET but the minimum impact on its leakage current. However, the device parameters such as carrier concentration and radius of the channel contributed significant impact on the threshold voltage, on-state current and leakage current. The simulated result of the optimized device for N-MOS and P-MOS indicates that its electrical properties enhanced significantly. For N-MOS, the threshold voltage, current-ratio and subthreshold and drain induced barrier lowering were calculated as 0.350V, 1.606, 60 mV and 40.04 mV/dec, respectively, meanwhile for P-MOS, the threshold voltage, current-ratio and subthreshold and drain induced barrier lowering were obtained as 0.355V, 4.132, 60 mV and 60.6 mV/dec, accordingly. These results revealed that the Junctionless GAA MOSFET could meet the requirement set by IRDS for a low power application which can offer minimum leakage current and suitable to be used for an inverter application

Finite element analysis of silicon nanowire array based SAW gas sensor

This work presents the design and finite element analysis of a surface acoustic wave (SAW)-based sensor for the detection of volatile organic compound (VOC) gases. The effect of silicon nanowire array (SiNWA) on a 128º YX-lithium niobate (LiNbO3) substrate for sensing the VOC gases was simulated using COMSOL Multiphysics. The frequency response was investigated in relation to changes in the SiNWA sensitive layer and VOC gas concentration. The resonant frequency of the SAW device was also evaluated, and simulation results were obtained after being exposed to 100ppm concentration of VOC gas. It was determined that the frequency increased, after the sensor was exposed to VOC gases. In general, extending the length of the SiNWA enhances the sensor's sensitivity

Explicit charge-based model for strained-silicon gate-all-around mosfet including quantum and short channel effects

In the recent development of advanced nanoelectronic devices, strain application on silicon Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) has been identified as a key factor towards the improvement of device performance. Strainedsilicon is preferred due to less impact of the short channel effects, enhanced the carrier mobility and lower the threshold voltage . Besides, strained-silicon can be applied to the non-planar multi-gate structures such as Gate All Around (GAA) MOSFET. Chargebased modelling (Qm) technique is widely been used for unstrained GAA MOSFET. However, in this research work, the approach is exercised for strained-silicon GAA MOSFET and subsequently to characterise its electrical behaviour in long and short channel devices. The model is solved explicitly using a smoothing function to avoid the convergence issue compared to the numerical model. For one-dimensional (1D) strained silicon GAA MOSFET, the geometry scaling in the radial direction which includes the radius and oxide layer thickness of the silicon layer can contribute to the quantum effects. In order to improve the accuracy of the model, quantum capacitance and threshold voltage were integrated into the long channel explicit model to facilitate the quantum effect. For the short channel model, second-order physical effects were included such as velocity saturation, channel length modulation and threshold voltage roll-off to resemble the behaviour of the short channel device. Afterwards, the results from the constructed models are compared against the Technology Computer Aided Design (TCAD) simulation and published data. A good agreement was achieved between model and simulated data indicates that the physical mechanisms of quantum and short channel effects used in the model are valid. Besides, it is shown that the existence of quantum starts to exhibit for radius and oxide layer less than 10 nm and 14 nm, respectively, regardless of the channel length being used in the device structure. For device optimisation, gate stack with SiO2�H fO2 configuration is preferred due to its smaller leakage current. The most optimised dimension is attained with the gate length of 40 nm attributed to the enhanced overall electrical performances. The extracted threshold voltage and on-state current obtained as 0:164 V and 8000 uA/um, accordingly, where the values outperform the IRDS benchmarking for low power application device

Heat-assisted μ-electrical discharge machining of silicon

Micro-electrical discharge machining (µEDM) is an unconventional machining method that is suitable for machining of conductive materials including highly doped silicon (Si) wafers. This paper reports a novel method of heat-assisted µEDM machining of Si wafers by varying the temperature to increase the electrical conductivity of Si. In order to achieve this condition, a ceramic heater is used to heat the Si wafers within the temperature range of 30–250 °C. In this study, the machining performances in terms of the material removal rate, tool wear rate, surface quality, and materials characterization have been investigated accordingly. The machining performance of p-type (1–10 O cm) Si wafers was investigated to machine a cavity based on different temperatures with a constant discharge energy of 50 µJ and a feed rate of 50 µm/min. The results indicated that increasing the machining temperature allowed achieving a higher material removal rate, lower tool wear rate, and lower surface roughness. The highest material removal rate of 1.43 × 10-5 mm3/s and a surface roughness of 1.487 µm were achieved at 250 °C. In addition, the material removal rate increased by a factor of ~16 times compared to the results obtained at the lowest temperature, 30 °C, and the Raman spectroscopy analysis revealed that no significant changes occurred in the Si structure before and after machining

Heat-assisted μ-electrical discharge machining of silicon

Micro-electrical discharge machining (μEDM) is an unconventional machining method that is suitable for machining of conductive materials including highly doped silicon (Si) wafers. This paper reports a novel method of heat-assisted μEDM machining of Si wafers by varying the temperature to increase the electrical conductivity of Si. In order to achieve this condition, a ceramic heater is used to heat the Si wafers within the temperature range of 30–250 °C. In this study, themachining performances in terms of the material removal rate, tool wear rate, surface quality, and materials characterization have been investigated accordingly. The machining performance of p-type (1–10 Ω cm) Si wafers was investigated to machine a cavity based on different temperatures with a constant discharge energy of 50 μJ and a feed rate of 50 μm/min. The results indicated that increasing the machining temperature allowed achieving a higher material removal rate, lower tool wear rate, and lower surface roughness. The highest material removal rate of 1.43 × 10−5 mm3/s and a surface roughness of 1.487 μm were achieved at 250 °C. In addition, the material removal rate increased by a factor of ~16 times compared to the results obtained at the lowest temperature, 30 °C, and the Raman spectroscopy analysis revealed that no significant changes occurred in the Si structure before and after machining