High efficiency architecture of ESCOT with pass concurrent context modeling scheme for scalable video coding

[[abstract]]In this work, we propose a high efficiency hardware architecture of embedded sub-band coding with optimal truncation (ESCOT) with pass concurrent context modeling (PCCM) scheme for wavelet-based scalable video coding (SVC). PCCM can merge the three-pass process of bit-plane coding into a single pass process. It improves the efficiency of the ESCOT algorithm and reduces the frequencies of memory access, which can reduce the power consumption. Furthermore we use the parallel architecture scheme of PCCM to encode 4 samples concurrently, which improves the operation speed and can reduce 40% of internal memory requirement. We use Artison TSMC 0.18 mum 1P6M standard cell library to design and implement the proposed concurrent context modeling. The simulation results indicate that PCCM can have an operation speedup of 9.5 compared to the standard context modeling of ESCOT, and it can operate for 1080 p with frame rate of 30 fps at clock rate of 125 MHz.[[conferencetype]]國際[[conferencedate]]20080518~20080521[[iscallforpapers]]Y[[conferencelocation]]Seattle, WA, US

The design of a delta-sigma modulator with low clock feedthrough noise, op-amp gain compensation, and more correctly transferring charges between capacitors

[[abstract]]The performance of a delta-sigma modulator (Δ ΣM) is degraded due to the low op-amp gain, the clock feedthrough noise, and the right or fault of charge transferring between capacitors. Hurst et al. in 1993 suggested an architecture which uses reduced sensitivity to the op-amp gain. Since the low op-amp gain is much easier to design and makes the design of a Δ ΣM become very easy. However, they do not overcome the noise effect of the Δ ΣM. Here, another design is proposed and the effect of noise is reduced[[conferencetype]]國際[[conferencedate]]19970609~19970612[[conferencelocation]]Hong Kon

High-speed EBCOT with dual context-modeling coding architecture for JPEG2000

[[abstract]]This work presents a parallel context-modeling coding architecture and a matching arithmetic coder (MQ coder) for the embedded block coding (EBCOT) unit of the JPEG2000 encoder. The tier-1 of the EBCOT consumes most of the computation time in a JPEG2000 encoding system, and the proposed parallel architecture can increase the throughput rate of the context-modeling. To match the high throughput rate of the parallel context-modeling architecture, and efficient pipelined architecture for context-based adaptive arithmetic encoder is proposed. This encoder of JPEG2000 can work at 185MHz to encode one symbol each cycle. Compared with the conventional context-modeling architecture, our parallel architecture can decrease the execution time about 25%.[[conferencetype]]國際[[conferencedate]]20040523~20040526[[conferencelocation]]溫哥華, 加拿

The design and implementation of an asynchronous radix-2 non-restoring 32-b/32-b ring divider, 2, pp.173-176

[[abstract]]Division operation is very important in computer systems. Conventionally synchronous techniques are applied to implement the divider. In this paper we propose a new asynchronous architecture for the divider. In this asynchronous scheme, the architecture is simple and is very easy to implement in VLSI. With this asynchronous architecture, we use TSMC's 0.6 um SPDM process to design a 32-b/32-b radix-2 non-restoring divider. The HSPICE simulation shows that this divider can finish a 32-b/32-b division operation in 3.7 ns to 160.2 ns[[conferencetype]]國際[[conferencedate]]19980531~19980603[[conferencelocation]]Monterey, CA, US

[[alternative]]The Design and Implementation of High Throughput Rate Viterbi Decoder

[[abstract]]此篇論文主要在陳述一種新的維特比解碼器(Viterbi decoder)的架構，目的在 提高原有IS-95, IS-2000, 8021.x的傳輸率。就原IS-95標準，其輸入頻率為10 MHz，而其傳輸率為1.22 Mbps，如果使用此架構，可將其傳輸率提升至40 Mbps，其改善倍率將近32倍。如果以IS-2000為比較(3.1 Mbps)，此架構的改善 倍率，亦可達到12倍之多。而如果以現存的802.11 a/b/g，可將其原有的輸入觸 發頻率40 MHz降至10 MHz，其輸傳輸率仍可維持在27 Mbps，甚至達到40 Mbps。 並且在未來的802.11n標準下，其傳輸率必須達到100 Mbps，如輸入頻率維持在 40 MHz，此架構可提供到160 Mbps的傳輸率，仍然遠超過802.11n的標準。而且 也可大幅減少生還者路徑(Trace back unit)單元所佔積體電路的面積。[[sponsorship]]雲林科技大學工程學院電機工程系；影音壓縮推動聯盟；工研院光電所; 雲林科技大學資訊工程所；工研院電通所；中華電信研究所; 行政院國家科學委員會工程科技推展中心；工研院電子所；資訊工業策進會[[conferencetype]]國內[[conferencedate]]20051117~20051118[[booktype]]紙本[[iscallforpapers]]Y[[conferencelocation]]雲林縣, 臺

[[alternative]]A New Mask-Based Algorithm for 2-D Discrete Wavelet Transforms Processor

[[abstract]]在本論文中，我們透過目前多媒體技術常用的離散小波轉換(Discrete wavelet transform, DWT) 演算法，提出了一種新式二維離散小波轉換影像處理器—遮罩式(Mask-based)結構設計；在演算法設計上，我們特別針對離散小波轉換架構中常用的提昇式(Lifting-based)結構去解決它一直存在的臨界路徑(Critical Path)與潛在時間(Latency)過長之問題為改善目標；此演算法是藉由適當的係數設計與利用空間域(Spatial domain)上影像的相關聯性，使得遮罩式演算法比提昇式演算法在處理完二維影像時的運算上可以更即時且減少資料輸出延遲的時間；它與提昇式5/3無失真離散小波轉換器運算出來的影像品質與數值是完全相同的，而且也可很方便的作二維多階的運算。它可適用於JPEG 2000，MPEG-4和SVC的即時影像/視訊處理。[[abstract]]This work presents novel algorithms to improve the critical issue of 2-D Lifting-based discrete wavelet transform (DWT). The algorithm is based on our proposed 2-D Mask-based DWT algorithm processing to achieve high-speed operation. The proposed 2-D Mask-based DWT algorithm has the advantages of fast computational time, regular signal coding, shorter critical path, and reduced latency time. Meanwhile, our 2-D DWT can also provide embedded symmetric boundary extension function and regular data flow. It can be applied to real-time image/video operating such as JPEG 2000, MPEG-4, and SVC applications.[[sponsorship]]崑山科技大學；資訊工業策進會；中華民國資訊安全學會[[conferencetype]]國內[[conferencedate]]20051215~20051216[[booktype]]紙本[[iscallforpapers]]Y[[conferencelocation]]臺南, 臺