8,970 research outputs found
An efficient hardware architecture for H.264 adaptive deblocking filter algorithm
This paper presents an efficient hardware architecture for real-time implementation of adaptive deblocking filter algorithm used in H.264 video coding standard. This hardware is designed to be used as part of a complete H.264 video coding system for portable applications. We use a novel edge filter ordering in a Macroblock to prevent the deblocking filter hardware from unnecessarily waiting for the pixels that will be filtered become available. The proposed architecture is implemented in Verilog HDL. The Verilog RTL code is verified to work at 72 MHz in a Xilinx Virtex II FPGA. The FPGA implementation can code 30 CIF frames (352x288) per second
Odd q-State Clock Spin-Glass Models in Three Dimensions, Asymmetric Phase Diagrams, and Multiple Algebraically Ordered Phases
Distinctive orderings and phase diagram structures are found, from
renormalization-group theory, for odd q-state clock spin-glass models in d=3
dimensions. These models exhibit asymmetric phase diagrams, as is also the case
for quantum Heisenberg spin-glass models. No finite-temperature spin-glass
phase occurs. For all odd , algebraically ordered
antiferromagnetic phases occur. One such phase is dominant and occurs for all
. Other such phases occupy small low-temperature portions of the
phase diagrams and occur for . All algebraically
ordered phases have the same structure, determined by an attractive
finite-temperature sink fixed point where a dominant and a subdominant pair
states have the only non-zero Boltzmann weights. The phase transition critical
exponents quickly saturate to the high q value.Comment: Published version, 9 pages, 10 phase diagrams, 5 figures, 1 tabl
Overfrustrated and Underfrustrated Spin-Glasses in d=3 and 2: Evolution of Phase Diagrams and Chaos Including Spin-Glass Order in d=2
In spin-glass systems, frustration can be adjusted continuously and
considerably, without changing the antiferromagnetic bond probability p, by
using locally correlated quenched randomness, as we demonstrate here on
hypercubic lattices and hierarchical lattices. Such overfrustrated and
underfrustrated Ising systems on hierarchical lattices in d=3 and 2 are
studied. With the removal of just 51 % of frustration, a spin-glass phase
occurs in d=2. With the addition of just 33 % frustration, the spin-glass phase
disappears in d=3. Sequences of 18 different phase diagrams for different
levels of frustration are calculated in both dimensions. In general,
frustration lowers the spin-glass ordering temperature. At low temperatures,
increased frustration favors the spin-glass phase (before it disappears) over
the ferromagnetic phase and symmetrically the antiferromagnetic phase. When any
amount, including infinitesimal, frustration is introduced, the chaotic
rescaling of local interactions occurs in the spin-glass phase. Chaos increases
with increasing frustration, as seen from the increased positive value of the
calculated Lyapunov exponent , starting from when
frustration is absent. The calculated runaway exponent of the
renormalization-group flows decreases with increasing frustration to
when the spin-glass phase disappears. From our calculations of entropy and
specific heat curves in d=3, it is seen that frustration lowers in temperature
the onset of both long- and short-range order in spin-glass phases, but is more
effective on the former. From calculations of the entropy as a function of
antiferromagnetic bond concentration p, it is seen that the ground-state and
low-temperature entropy already mostly sets in within the ferromagnetic and
antiferromagnetic phases, before the spin-glass phase is reached.Comment: Published version, 18 phase diagrams, 12 figures, 10 page
A reconfigurable frame interpolation hardware architecture for high definition video
Since Frame Rate Up-Conversion (FRC) is started to be used in recent consumer electronics products like High Definition TV, real-time and low cost implementation of FRC algorithms has become very important. Therefore, in this
paper, we propose a low cost hardware architecture for realtime implementation of frame interpolation algorithms. The proposed hardware architecture is reconfigurable and it allows adaptive selection of frame interpolation algorithms for each Macroblock. The proposed hardware architecture is implemented in VHDL and mapped to a low cost Xilinx XC3SD1800A-4 FPGA device. The implementation results
show that the proposed hardware can run at 101 MHz on this FPGA and consumes 32 BRAMs and 15384 slices
A High performance and low cost hardware arcitecture for H.264 transform and quantization algorithms
In this paper, we present a high performance and low cost hardware architecture for real-time implementation of forward transform and quantization and inverse transform and quantization algorithms used in H.264 / MPEG4 Part 10 video coding standard. The hard-ware architecture is based on a reconfigurable datapath with only one multiplier. This hardware is designed to be used as part of a complete low power H.264 video coding system for portable appli-cations. The proposed architecture is implemented in Verilog HDL. The Verilog RTL code is verified to work at 81 MHz in a Xilinx Virtex II FPGA and it is verified to work at 210 MHz in a 0.18´ ASIC implementation. The FPGA and ASIC implementations can code 27 and 70 VGA frames (640x480) per second respectively
Characterization of the potential smoothness of one-dimensional Dirac operator subject to general boundary conditions and its Riesz basis property
The one-dimensional Dirac operator with periodic potential , where
subject to periodic, antiperiodic or
a general strictly regular boundary condition has discrete spectrums. It
is known that, for large enough in the disc centered at of radius
1/4, the operator has exactly two (periodic if is even or antiperiodic if
is odd) eigenvalues and (counted according to
multiplicity) and one eigenvalue corresponding to the boundary
condition . We prove that the smoothness of the potential could be
characterized by the decay rate of the sequence ,
where and
Furthermore, it is shown that the Dirac
operator with periodic or antiperiodic boundary condition has the Riesz basis
property if and only if is finite.Comment: 29 pages, no figur
An efficient hardware architecture for H.264 intra prediction algorithm
In this paper, we present an efficient hardware architecture for real-time implementation of intra prediction algorithm used in H.264 / MPEG4 Part 10 video coding standard. The hardware design is based on a novel organization of the intra prediction equations. This hardware is designed to be used as part of a complete H.264 video coding system for portable applications. The proposed architecture is implemented in Verilog HDL. The Verilog RTL code is verified to work at 90 MHz in a Xilinx Virtex II FPGA. The FPGA implementation can process 27 VGA frames (640x480) per second
Multicriteria sustainability evaluation of transport networks for selected European countries
As an essential economic activity, transportation has complex interactions with the environment and society. Since the concept of sustainable development has become one of the top priorities for nations, there has been a growing interest in evaluating the performance of transport systems with respect to sustainability issues. The main purpose of this study is to introduce a decision making framework to assess the sustainability of the transport networks in a multidimensional setting and a technique to identify non-compromise alternatives. We also propose an elucidation technique to identify according to which criteria a system needs to be improved and how much improvement is required to attain a certain level of sustainability. The proposed methods are applied to a set of selected European countries within a case study
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