Disengaged Scheduling for Fair, Protected Access to Fast Computational Accelerators

Today’s operating systems treat GPUs and other computational accelerators as if they were simple devices, with bounded and predictable response times. With accelerators assuming an increasing share of the workload on modern machines, this strategy is already problematic, and likely to become untenable soon. If the operating system is to enforce fair sharing of the machine, it must assume responsibility for accelerator scheduling and resource management. Fair, safe scheduling is a particular challenge on fast accelerators, which allow applications to avoid kernel-crossing overhead by interacting directly with the device. We propose a disengaged scheduling strategy in which the kernel intercedes between applications and the accelerator on an infrequent basis, to monitor their use of accelerator cycles and to determine which applications should be granted access over the next time interval. Our strategy assumes a well defined, narrow interface exported by the accelerator. We build upon such an interface, systematically inferred for the latest Nvidia GPUs. We construct several example schedulers, including Disengaged Timeslice with overuse control that guarantees fairness and Disengaged Fair Queueing that is effective in limiting resource idleness, but probabilistic. Both schedulers ensure fair sharing of the GPU, even among uncooperative or adversarial applications; Disengaged Fair Queueing incurs a 4 % overhead on average (max 18%) compared to direct devic

Procesamiento distribuido y paralelo de bajo costo basado en cloud&movil

Actualmente el procesamiento intensivo se realiza a través de estructuras HPC híbridas (Grid, Cluster, Cloud) utilizando procesadores de arquitectura x86 y GPUs Nvidia, AMD o Intel, incurriendo en altísimos costos económicos y energéticos. Sin embargo, gracias a la evolución constante del hardware y con el advenimiento de los dispositivos móviles/microcomputadores con CPUs/GPUs ARM acompañado de la masividad de los mismos es posible pensar en una solución de bajo costo y consumo energético para solventar este tipo de problemas. Estos dispositivos incrementan su capacidad, eficiencia, estabilidad y potencia a diario, mientras ganan mercado, conservando un bajo costo, tamaño y consumo energético. A su vez, presentan lapsos de ociosidad, lo que representa una gran capacidad de recursos desaprovechados. Por tal motivo, el objetivo de este trabajo es presentar un prototipo de arquitectura distribuida dinámica, escalable y redundante geográficamente para explotar esta disponibilidad y realizar procesamiento intensivo aprovechando recursos y reduciendo costos.XVIII Workshop de Procesamiento Distribuido y Paralelo (WPDP

Track pattern-recognition on GPGPUs in the LHCb experiment

The LHCb experiment is entering in its upgrading phase, with its detector and read-out system re-designed to cope with the increased LHC energy after the long shutdown of 2018. In this upgrade, a trigger-less data acquisition is being developed to read-out the full detector at the bunch-crossing rate of 40 MHz. In particular, the High Level Trigger (HLT) system has to be heavily revised. Since the small LHCb event size (about 100 kB), many-core architectures such as General Purpose Graphics Processing Units (GPGPUs) and multi-core CPUs can be used to process many events in parallel for real-time selection, and may offer a solution for reducing the cost of the HLT farm. Track reconstruction and vertex finding are the more time-consuming applications running in HLT and therefore are the first to be ported on many-core. In this talk we present our implementation of the existing tracking algorithms on GPGPU, discussing in detail the case of the VErtex LOcator detector (VELO), and we show the achieved performances. We discuss also other tracking algorithms that can be used in view of the LHCb upgra