1,231 research outputs found
Concatenated Turbo/LDPC codes for deep space communications: performance and implementation
Deep space communications require error correction codes able to reach extremely low bit-error-rates, possibly with a steep waterfall region and without error floor. Several schemes have been proposed in the literature to achieve these goals. Most of them rely on the concatenation of different codes that leads to high hardware implementation complexity and poor resource sharing. This work proposes a scheme based on the concatenation of non-custom LDPC and turbo codes that achieves excellent error correction performance. Moreover, since both LDPC and turbo codes can be decoded with the BCJR algorithm, our preliminary results show that an efficient hardware architecture with high resource reuse can be designe
Flexible LDPC Decoder Architectures
Flexible channel decoding is getting significance with the increase in number of wireless standards and modes within a standard. A flexible channel decoder is a solution providing interstandard and intrastandard support without change in hardware. However, the design of efficient implementation of flexible low-density parity-check (LDPC) code decoders satisfying area, speed, and power constraints is a challenging task and still requires considerable research effort. This paper provides an overview of state-of-the-art in the design of flexible LDPC decoders. The published solutions are evaluated at two levels of architectural design: the processing element (PE) and the interconnection structure. A qualitative and quantitative analysis of different design choices is carried out, and comparison is provided in terms of achieved flexibility, throughput, decoding efficiency, and area (power) consumptio
VLSI implementation of a multi-mode turbo/LDPC decoder architecture
Flexible and reconfigurable architectures have gained wide popularity in the communications field. In particular, reconfigurable architectures for the physical layer are an attractive solution not only to switch among different coding modes but also to achieve interoperability. This work concentrates on the design of a reconfigurable architecture for both turbo and LDPC codes decoding. The novel contributions of this paper are: i) tackling the reconfiguration issue introducing a formal and systematic treatment that, to the best of our knowledge, was not previously addressed; ii) proposing a reconfigurable NoCbased turbo/LDPC decoder architecture and showing that wide flexibility can be achieved with a small complexity overhead. Obtained results show that dynamic switching between most of considered communication standards is possible without pausing the decoding activity. Moreover, post-layout results show that tailoring the proposed architecture to the WiMAX standard leads to an area occupation of 2.75 mm2 and a power consumption of 101.5 mW in the worst case
Improved Successive Cancellation Flip Decoding of Polar Codes Based on Error Distribution
Polar codes are a class of linear block codes that provably achieves channel
capacity, and have been selected as a coding scheme for generation
wireless communication standards. Successive-cancellation (SC) decoding of
polar codes has mediocre error-correction performance on short to moderate
codeword lengths: the SC-Flip decoding algorithm is one of the solutions that
have been proposed to overcome this issue. On the other hand, SC-Flip has a
higher implementation complexity compared to SC due to the required
log-likelihood ratio (LLR) selection and sorting process. Moreover, it requires
a high number of iterations to reach good error-correction performance. In this
work, we propose two techniques to improve the SC-Flip decoding algorithm for
low-rate codes, based on the observation of channel-induced error
distributions. The first one is a fixed index selection (FIS) scheme to avoid
the substantial implementation cost of LLR selection and sorting with no cost
on error-correction performance. The second is an enhanced index selection
(EIS) criterion to improve the error-correction performance of SC-Flip
decoding. A reduction of in the implementation cost of logic elements
is estimated with the FIS approach, while simulation results show that EIS
leads to an improvement on error-correction performance improvement up to
dB at a target FER of .Comment: This version of the manuscript corrects an error in the previous
ArXiv version, as well as the published version in IEEE Xplore under the same
title, which has the DOI:10.1109/WCNCW.2018.8368991. The corrections include
all the simulations of SC-Flip-based and SC-Oracle decoders, along with
associated comments in-tex
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