A physics-based approach for power integrity in multi-layered PCBs

Developing a power distribution network (PDN) for ASICs and ICs to achieve the low-voltage ripple specifications for current digital designs is challenging with the high-speed and low-voltage ICs. Present methods are typically guided by best engineering practices for low impedance looking into the PDN from the IC. A pre-layout design methodology for power integrity in multi-layered PCB PDN geometry is proposed in the thesis. The PCB PDN geometry is segmented into four parts and every part is modelled using different methods based on the geometry details of the part. Physics-based circuit models are built for every part and the four parts are re-assembled into one model. The influence of geometry details is clearly revealed in this methodology. Based on the physics-based circuit mode, the procedures of using the pre-layout design methodology as a guideline during the PDN design is illustrated. Some common used geometries are used to build design space, and the design curves with the geometry details are provided to be a look up library for engineering use. The pre-layout methodology is based on the resonant cavity model of parallel planes for the cavity structures, and parallel-plane PEEC (PPP) for the irregular shaped plane inductance, and PEEC for the decoupling capacitor connection above the top most or bottom most power-return planes. PCB PDN is analyzed based on the input impedance looking into the PCB from the IC. The pre-layout design methodology can be used to obtain the best possible PCB PDN design. With the switching current profile, the target impedance can be selected to evaluate the PDN performance, and the frequency domain PDN input impedance can be used to obtain the voltage ripple in the time domain to give intuitive insight of the geometry impact on the voltage ripple --Abstract, page iii

Peec-Based On-Chip Pdn Impedance Modeling using Layered Green\u27s Function

This paper presents an impedance model of on-chip power distribution network (PDN), which is an efficient criterion for estimating simultaneous switching noises (SSNs) on 3-D integrated circuit (IC). The impedance of on-chip PDN, including the effect of silicon substrate, is accurately modeled based on partial element equivalent circuit (PEEC) and layered Green\u27s function (LGF). The equivalent circuit model of PDN is extracted based on the physical dimensions and electrical material characteristic of PDN at first. And then the LGF is used to consider the effect of silicon substrate for improving the accuracy of on-chip PDN impedance model. The effectiveness of proposed model has been validated by full wave simulation. The high order resonance of PDN impedance can also be accurately predicted

System SI/PI modeling and analysis

A physics-based circuit modeling methodology for 3D IC/packages is proposed here. The method is based on partial element equivalent circuit (PEEC) and layered Green\u27s function (LGF). The LGFs are calculated from discrete complex image method (DCIM) with three terms, direct coupling, complex images, and surface wave, extracted to analyze the wave behavior. The dominate terms for LGFs are analyzed for four stack-ups in 3D IC/packages. Analytical formulas that include the contribution of complex images are proposed for partial capacitance calculation, with the complex image extracted from LGFs. A chip PDN geometry is used to illustrate the use of LGF in PEEC to validate the proposed method. A good match is observed between the input impedance from the proposed method and full wave simulation. A physics-based circuit modeling methodology for system-level power integrity (PI) analysis and design is presented herein. The modeling methodology is based on representing the current paths in the power distribution network (PDN) with appropriate circuits based on cavity model and plane-pair Partial Element Equivalent Circuit (PEEC). The PDN input impedance looking from on-chip sources can be computed. A commercial simulation tool is used to corroborate the modeling approach where the system consists of a commercial IC, a complex organic package and a very high-layer-count printed circuit board. Two types of circuit models are proposed from the methodology with physical correspondence maintained in the circuit elements. The circuits can be used to analyze the geometry impact on the PDN impedance and explore design improvements. Voltage ripple simulations are conducted with the circuit models. The simulated results correlated with measurements --Abstract, page iii

Green\u27s Functions in Lossy Multi-Layer Dielectrics for 3D IC/Packaging Applications

Green\u27s function in lossy multi-layer dielectrics is presented using DCIM method for 3D IC/packaging in this paper. Loss effects in layered medium are analysed through the components extracted from DCIM. The proposed layered Green\u27s function can be used for 3D IC and packaging applications

Design Tips

Welcome to Design Tips! This article will examine how to minimize the inductance associated with mounting decoupling capacitors to power/ground-reference planes. The configuration can have a significant impact on the apparent inductance. The total number of capacitors can be reduced with careful configuration control

UniFL: Accelerating Federated Learning Using Heterogeneous Hardware Under a Unified Framework

Federated learning (FL) is now considered a critical method for breaking down data silos. However, data encryption can significantly increase computing time, limiting its large-scale deployment. While hardware acceleration can be an effective solution, existing research has largely focused on a single hardware type, which hinders the acceleration of FL across the various heterogeneous hardware of the participants. In light of this challenge, this paper proposes a novel FL acceleration framework that supports diverse types of hardware. Firstly, we conduct an analysis of the key elements of FL to clarify our accelerator design goals. Secondly, a unified acceleration framework is proposed, which divides FL into four layers, providing a basis for the compatibility and implementation of heterogeneous hardware acceleration. After that, based on the physical properties of three mainstream acceleration hardware, i.e., GPU, ASIC and FPGA, the architecture design of corresponding heterogeneous accelerators under the framework is detailed. Finally, we validate the effectiveness of the proposed heterogeneous hardware acceleration framework through experiments. For specific algorithms, our implementation achieves a state of the art acceleration effect compared to previous work. For the end-to-end acceleration performance, we gain $12\times$ , $7.7\times$ and $2.2\times$ improvement on GPU, ASIC and FPGA respectively, compared to CPU in large-scale vertical linear regression training tasks

Effect of Narrow Power Fills on PCB PDN Noise

The printed circuit board (PCB) power delivery network (PDN) performance has become critical with the reducing margins on power noise. This paper deals with a specific question about the size of the power area fill used to route the power current from the dc regulator to integrated circuit(IC), and also used for connecting to the decoupling capacitors. With increased PCB real estate costs, narrow power fills are required, which results in an increase in the connection inductance of decoupling capacitors. This paper uses a proven lumped circuit model extraction procedure, based on the first principle resonant cavity model, to demonstrate the effect of narrow and wide area fills used in typical PCB PDN designs. The frequency domain results thus obtained are used with typical IC current draw profiles to show the impact on the noise voltage developed at the IC. Some design guidelines and conclusions are drawn from these results

Genome-Wide Identification of the CER Gene Family and Significant Features in Climate Adaptation of Castanea mollissima

The plant cuticle is the outermost layer of the aerial organs and an important barrier against biotic and abiotic stresses. The climate varies greatly between the north and south of China, with large differences in temperature and humidity, but Chinese chestnut is found in both regions. This study investigated the relationship between the wax layer of chestnut leaves and environmental adaptation. Firstly, semi-thin sections were used to verify that there is a significant difference in the thickness of the epicuticular wax layer between wild chestnut leaves in northwest and southeast China. Secondly, a whole-genome selective sweep was used to resequence wild chestnut samples from two typical regional populations, and significant genetic divergence was identified between the two populations in the CmCER1-1, CmCER1-5 and CmCER3 genes. Thirty-four CER genes were identified in the whole chestnut genome, and a series of predictive analyses were performed on the identified CmCER genes. The expression patterns of CmCER genes were classified into three trends—upregulation, upregulation followed by downregulation and continuous downregulation—when chestnut seedlings were treated with drought stress. Analysis of cultivars from two resource beds in Beijing and Liyang showed that the wax layer of the northern variety was thicker than that of the southern variety. For the Y-2 (Castanea mollissima genome sequencing material) cultivar, there were significant differences in the expression of CmCER1-1, CmCER1-5 and CmCER3 between the southern variety and the northern one-year-grafted variety. Therefore, this study suggests that the CER family genes play a role in environmental adaptations in chestnut, laying the foundation for further exploration of CmCER genes. It also demonstrates the importance of studying the adaptation of Chinese chestnut wax biosynthesis to the southern and northern environments

Impact of Chip and Interposer PDN to Eye Diagram in High Speed Channels

The paper applies the combined SI-PI co-simulation to on chip high speed interconnects. A complete model of chip and interposer PDN is developed and, together to a lumped model of the PCB and package PDN, it is employed to supply I/O drivers for HBM traces laid out on silicon interposer. A comprehensive analysis is carried out highlighting the impact of the decoupling capacitor placement and their corresponding parasitic inductance on the supply voltage ripple and on the output eye diagram at the signal receivers

Additional file 2 of Shenkang protects renal function in diabetic rats by preserving nephrin expression

Additional file 2: Supplemental table 1. Tests of group differences between diabetic rats in randomized groups. Supplemental table 2. Pairwise group comparison of diabetic rats in randomized group