280 research outputs found
Bias analysis in mode-based Kalman filters for stochastic hybrid systems
Doctor of PhilosophyDepartment of Electrical and Computer EngineeringBalasubramaniam NatarajanStochastic hybrid system (SHS) is a class of dynamical systems that experience interaction of both discrete mode and continuous dynamics with uncertainty. State estimation for SHS has attracted research interests for decades with Kalman filter based solutions dominating the area. Mode-based Kalman filter is an extended version of the traditional Kalman filter for SHS. In general, as Kalman filter is unbiased for non-hybrid system estimation, prior research efforts primarily focus on the behavior of error covariance. In SHS state estimate, mode mismatch errors could result in a bias in the mode-based Kalman filter and have impacts on the continuous state estimation quality. The relationship between mode mismatch errors and estimation stability is an open problem that this dissertation attempts to address. Specifically, the probabilistic model of mode mismatch errors can be independent and identically distributed (i.i.d.), correlated across different modes and correlated across time. The proposed approach builds on the idea of modeling the bias evolution as a transformed system. The statistical convergence of the bias dynamics is then mapped to the stability of the transformed system. For each specific model of the mode mismatch error, the system matrix of the transformed system varies which results in challenges for the stability analysis. For the first time, the dissertation derives convergence conditions that provide tolerance regions for the mode mismatch error for three mode mismatch situations. The convergence conditions are derived based on generalized spectral radius theorem, Lyapunov theorem, Schur stability of a matrix polytope and interval matrix method. This research is fundamental in nature and its application is widespread. For example, the spatially and timely correlated mode mismatch errors can effectively capture cyber-attacks and communication link impairments in a cyber-physical system. Therefore, the theory and techniques developed in this dissertation can be used to analyze topology errors in any networked system such as smart grid, smart home, transportation, flight management system etc. The main results provide new insights on the fidelity in discrete state knowledge needed to maintain the performance of a mode-based Kalman filter and provide guidance on design of estimation strategies for SHS
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
In digital IC design, compared with post-synthesis netlists or layouts, the
early register-transfer level (RTL) stage offers greater optimization
flexibility for both designers and EDA tools. However, timing information is
typically unavailable at this early stage. Some recent machine learning (ML)
solutions propose to predict the total negative slack (TNS) and worst negative
slack (WNS) of an entire design at the RTL stage, but the fine-grained timing
information of individual registers remains unavailable. In this work, we
address the unique challenges of RTL timing prediction and introduce our
solution named RTL-Timer. To the best of our knowledge, this is the first
fine-grained general timing estimator applicable to any given design. RTL-Timer
explores multiple promising RTL representations and proposes customized loss
functions to capture the maximum arrival time at register endpoints.
RTL-Timer's fine-grained predictions are further applied to guide optimization
in a standard synthesis flow. The average results on unknown test designs
demonstrate a correlation above 0.89, contributing around 3% WNS and 10% TNS
improvement after optimization.Comment: Published as a conference paper at Design Automation Conference (DAC)
202
SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model
The development of architecture specifications is an initial and fundamental
stage of the integrated circuit (IC) design process. Traditionally,
architecture specifications are crafted by experienced chip architects, a
process that is not only time-consuming but also error-prone. Mistakes in these
specifications may significantly affect subsequent stages of chip design.
Despite the presence of advanced electronic design automation (EDA) tools,
effective solutions to these specification-related challenges remain scarce.
Since writing architecture specifications is naturally a natural language
processing (NLP) task, this paper pioneers the automation of architecture
specification development with the advanced capabilities of large language
models (LLMs). Leveraging our definition and dataset, we explore the
application of LLMs in two key aspects of architecture specification
development: (1) Generating architecture specifications, which includes both
writing specifications from scratch and converting RTL code into detailed
specifications. (2) Reviewing existing architecture specifications. We got
promising results indicating that LLMs may revolutionize how these critical
specification documents are developed in IC design nowadays. By reducing the
effort required, LLMs open up new possibilities for efficiency and accuracy in
this crucial aspect of chip design
BigData Express: Toward Schedulable, Predictable, and High-Performance Data Transfer (White Paper)
RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution
The automatic generation of RTL code (e.g., Verilog) using natural language
instructions and large language models (LLMs) has attracted significant
research interest recently. However, most existing approaches heavily rely on
commercial LLMs such as ChatGPT, while open-source LLMs tailored for this
specific design generation task exhibit notably inferior performance. The
absence of high-quality open-source solutions restricts the flexibility and
data privacy of this emerging technique. In this study, we present a new
customized LLM solution with a modest parameter count of only 7B, achieving
better performance than GPT-3.5 on two representative benchmarks for RTL code
generation. This remarkable balance between accuracy and efficiency is made
possible by leveraging our new RTL code dataset and a customized LLM algorithm,
both of which will be made fully open-source. Furthermore, we have successfully
quantized our LLM to 4-bit with a total size of 4GB, enabling it to function on
a single laptop with only slight performance degradation. This efficiency
allows the RTL generator to serve as a local assistant for engineers, ensuring
all design privacy concerns are addressed
MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
In modern VLSI design flow, the register-transfer level (RTL) stage is a
critical point, where designers define precise design behavior with hardware
description languages (HDLs) like Verilog. Since the RTL design is in the
format of HDL code, the standard way to evaluate its quality requires
time-consuming subsequent synthesis steps with EDA tools. This time-consuming
process significantly impedes design optimization at the early RTL stage.
Despite the emergence of some recent ML-based solutions, they fail to maintain
high accuracy for any given RTL design. In this work, we propose an innovative
pre-synthesis PPA estimation framework named MasterRTL. It first converts the
HDL code to a new bit-level design representation named the simple operator
graph (SOG). By only adopting single-bit simple operators, this SOG proves to
be a general representation that unifies different design types and styles. The
SOG is also more similar to the target gate-level netlist, reducing the gap
between RTL representation and netlist. In addition to the new SOG
representation, MasterRTL proposes new ML methods for the RTL-stage modeling of
timing, power, and area separately. Compared with state-of-the-art solutions,
the experiment on a comprehensive dataset with 90 different designs shows
accuracy improvement by 0.33, 0.22, and 0.15 in correlation for total negative
slack (TNS), worst negative slack (WNS), and power, respectively.Comment: To be published in the Proceedings of 42nd IEEE/ACM International
Conference on Computer-Aided Design (ICCAD), 202
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