An on-chip instrument for white blood cells classification based on a lens-less shadow imaging technique.

Routine blood tests provide important basic information for disease diagnoses. The proportions of three subtypes of white blood cells (WBCs), which are neutrophils, monocytes, lymphocytes, is key information for disease diagnosis. However, current instruments for routine blood tests, such as blood cell analyzers, flow cytometers, and optical microscopes, are cumbersome, time consuming and expensive. To make a smaller, automatic low-cost blood cell analyzer, much research has focused on a technique called lens-less shadow imaging, which can obtain microscopic images of cells in a lens-less system. Nevertheless, the efficiency of this imaging system is not satisfactory because of two problems: low resolution and imaging diffraction phenomena. In this paper, a novel method of classifying cells with the shadow imaging technique was proposed. It could be used for the classification of the three subtypes of WBCs, and the correlation of the results of classification between the proposed system and the reference system (BC-5180, Mindray) was 0.93. However, the instrument was only 10 × 10 × 10 cm, and the cost was less than $100. Depending on the lens-free shadow imaging technology, the main hardware could be integrated on a chip scale and could be called an on-chip instrument

High Dynamic Pixel Structure Based on an Adaptive Integrating Capacitor

Infrared image sensing technology has received widespread attention due to its advantages of not being affected by the environment, good target recognition, and high anti-interference ability. However, with the improvement of the integration of the infrared focal plane, the dynamic range of the photoelectric system is difficult to improve, that is, the restrictive trade-off between noise and full well capacity is particularly prominent. Since the capacitance of the inversion MOS capacitor changes with the gate–source voltage adaptively, the inversion MOS capacitor is used as the capacitor in the infrared pixel circuit, which can solve the contradiction between noise in low light and full well capacity in high light. To this end, a highly dynamic pixel structure based on adaptive capacitance is proposed, so that the capacitance of the infrared image sensor can automatically change from 6.5 fF to 37.5 fF as the light intensity increases. And based on 55 nm CMOS process technology, the performance parameters of an infrared image sensor with a 12,288 × 12,288 pixel array are studied. The research results show that a small-size pixel of 5.5 µm × 5.5 µm has a large full well capacity of 1.31 Me− and a variable conversion gain, with a noise of less than 0.43 e− and a dynamic range of more than 130 dB

High-Speed Fully Differential Two-Step ADC Design Method for CMOS Image Sensor

The application requirements of high frame rate CMOS image sensors (CIS) in the industry have not been satisfied due to the speed limitations in traditional single-slope and serial two-step analog-to-digital converters (ADCs). In this paper, a high-speed fully differential two-step ADC design method for CIS was proposed. The proposed method was based on differential ramp and time-to-digital conversion (TDC) technology. A parallel conversion mode was formed that is different from serial conversion, and the robustness of the system was ensured due to the existence of differential ramps. Aiming at the inconsistency between traditional TDC technology and single-slope ADC, a TDC technology based on level coding was proposed. The proposed technology achieves the TDC in the last clock cycle of analog-to-digital conversion, and realized a two-step conversion process at another level. This paper presents a complete circuit design, layout design, and test verification of the proposed design method based on the 55 nm 1P4M CMOS experimental platform. Under the design environment of the analog voltage of 3.3 V, the digital voltage of 1.2 V, the clock frequency of 100 MHz, and a dynamic input range of 1.6 V, this design was a 12-bit ADC with a conversion time of 480 ns, column-level power consumption of 62 μW, differential nonlinearity (DNL) of +0.6/−0.6 LSB, and integral nonlinearity (INL) of +1.2/−1.4 LSB. Furthermore, it achieved a signal-to-noise distortion ratio (SNDR) of 70.08 dB. The proposed design provided a large area array with a high frame rate, and compared with the existing advanced single-slope ADC, its conversion speed increased by more than 52%. It provides an effective solution for the implementation of high frame frequency CI

High-Precision Lens-Less Flow Cytometer on a Chip

We present a flow cytometer on a microfluidic chip that integrates an inline lens-free holographic microscope. High-speed cell analysis necessitates that cells flow through the microfluidic channel at a high velocity, but the image sensor of the in-line holographic microscope needs a long exposure time. Therefore, to solve this problem, this paper proposes an S-type micro-channel and a pulse injection method. To increase the speed and accuracy of the hologram reconstruction, we improve the iterative initial constraint method and propose a background removal method. The focus images and cell concentrations can be accurately calculated by the developed method. Using whole blood cells to test the cell counting precision, we find that the cell counting error of the proposed method is less than 2%. This result shows that the on-chip flow cytometer has high precision. Due to its low price and small size, this flow cytometer is suitable for environments far away from laboratories, such as underdeveloped areas and outdoors, and it is especially suitable for point-of-care testing (POCT)

An energy-efficient 2.5D through-silicon interposer I/O with self-adaptive adjustment of output-voltage swing

A self-adaptive output swing adjustment is introduced for the design of energy-efficient 2.5D through-silicon interposer (TSI) I/Os. Instead of transmitting signal with large voltage swing, Q-learning based self-adaptive adjustment is deployed to adjust I/O output-voltage swing under constraints of both power budget and bit error rate (BER). Experimental results show that the adaptive 2.5D TSI I/Os designed in 65nm CMOS can achieve an average of 13mW I/O power, 4GHz bandwidth and 3.25pJ/bit energy efficiency for one channel under 10−6 BER, which has 21.42%reduction of power and 14.47% energy efficiency improvement.Accepted versio

Improving ESD Protection Robustness Using SiGe Source/Drain Regions in Tunnel FET

Currently, a tunnel field-effect transistor (TFET) is being considered as a suitable electrostatic discharge (ESD) protection device in advanced technology. In addition, silicon-germanium (SiGe) engineering is shown to improve the performance of TFET-based ESD protection devices. In this paper, a new TFET with SiGe source/drain (S/D) regions is proposed, and its ESD characteristics are evaluated using technology computer aided design (TCAD) simulations. Under a transmission line pulsing (TLP) stressing condition, the triggering voltage of the SiGe S/D TFET is reduced by 35% and the failure current is increased by 17% in comparison with the conventional Si S/D TFET. Physical insights relevant to the ESD enhancement of the SiGe S/D TFET are provided and discussed