A new model of development of the mammalian ovary and follicles

Ovarian follicular granulosa cells surround and nurture oocytes, and produce sex steroid hormones. It is believed that during development the ovarian surface epithelial cells penetrate into the ovary and develop into granulosa cells when associating with oogonia to form follicles. Using bovine fetal ovaries (n = 80) we identified a novel cell type, termed GREL for Gonadal Ridge Epithelial-Like. Using 26 markers for GREL and other cells and extracellular matrix we conducted immunohistochemistry and electron microscopy and chronologically tracked all somatic cell types during development. Before 70 days of gestation the gonadal ridge/ovarian primordium is formed by proliferation of GREL cells at the surface epithelium of the mesonephros. Primordial germ cells (PGCs) migrate into the ovarian primordium. After 70 days, stroma from the underlying mesonephros begins to penetrate the primordium, partitioning the developing ovary into irregularly-shaped ovigerous cords composed of GREL cells and PGCs/oogonia. Importantly we identified that the cords are always separated from the stroma by a basal lamina. Around 130 days of gestation the stroma expands laterally below the outermost layers of GREL cells forming a sub-epithelial basal lamina and establishing an epithelial-stromal interface. It is at this stage that a mature surface epithelium develops from the GREL cells on the surface of the ovary primordium. Expansion of the stroma continues to partition the ovigerous cords into smaller groups of cells eventually forming follicles containing an oogonium/oocyte surrounded by GREL cells, which become granulosa cells, all enclosed by a basal lamina. Thus in contrast to the prevailing theory, the ovarian surface epithelial cells do not penetrate into the ovary to form the granulosa cells of follicles, instead ovarian surface epithelial cells and granulosa cells have a common precursor, the GREL cell.Katja Hummitzsch, Helen F. Irving-Rodgers, Nicholas Hatzirodos, Wendy Bonner, Laetitia Sabatier, Dieter P. Reinhardt, Yoshikazu Sado, Yoshifumi Ninomiya, Dagmar Wilhelm and Raymond J. Rodger

Charge transfer dynamics of 9-arylcarbazole studied by femtosecond transient absorption spectroscopy

In chemistry it is important to understand reaction mechanisms in solutions at a molecular level because most chemical reactions occur in solutions. Intramolecular charge transfer (ICT) in solutions is one of the most basic reactions, and the reaction mechanism of ICT is influenced by not only solute-solvent interactions but also geometrical change of solute molecule. 3,6-Bis(dimethylamino)-9-(4-cyanophenyl)carbazole (BANCC, Figure 1(a)) consists of an electron donor of the carbazole unit and an acceptor of the cyanophenyl unit, which are connected by a single bond[1]. In order to elucidate the ICT reaction mechanism of BANCC, we performed real time observation of the reaction process in various organic solvents by femtosecond transient absorption (TA) spectroscopy.Published versio

Design and Implementation of FPGA Circuits for High Speed Network Monitors

Due to the recent progress of the Internet, we need high-speed network monitors which can observe millions of packets per second. Since several types of network attacks occur, we need to modify monitoring facilities and their capacities depending on monitoring items and network speed. In this paper, we propose (1) a methodology for designing and implementing such network monitors flexibly and (2) a high-level synthesis technique which automatically synthesizes FPGA circuits from specifications of network monitors in a model called concurrent synchronous EFSMs. The proposed technique makes it possible to synthesize an FPGA circuit suitable for given monitoring items and parameters where the designer need not consider about how pipe-line processing and parallel processing should be adopted. We have developed a tool to automatically derive FPGA circuits and evaluated the speed and size of derived circuits

Design and Implementation of Priority Queuing Mechanism on FPGA using Concurrent Periodic EFSMs and Parametric Model Checking

In this paper, we propose a design and implementation method for priority queuing mechanisms on FPGAs. First, we describe behavior of WFQ (weighted fair queuing) with several parameters in a model called concurrent periodic EFSMs. Then, we derive a parameter condition for the concurrent EFSMs to execute their transitions without deadlocks in the specified time period repeatedly under the specified temporal constraints, using parametric model checking technique. From the derived parameter condition, we can decide adequate parameter values satisfying the condition, considering total costs of components. Based on the proposed method, high-reliable and high-performance WFQ circuits for gigabit networks can be synthesized on FPGAs

A Flexible and High-Reliable HW/SW Co-Design Method for Real-Time Embedded Systems

In this paper, we propose a flexible and high-reliable HW/SW co-design method for real-time systems consisting of multiple functional modules using general purpose components such as DSP, CPU and memory. In our method, we specify a system as a parallel composition of concurrent periodic EFSMs with timing constraints. As communication primitives among EFSMs, multi-way synchronization mechanism can be specified. Here, we propose a technique for efficient development of real-time embedded systems considering both reliability and cost-performance. For the purpose, using a parametric model checking technique, we derive a parameter condition which must hold for the system to proceed without deadlocks and satisfy given timing constraints. Based on the derived parameter condition and cost-performance characteristic of available components, an appropriate combination of components is automatically selected so that the total cost is minimized. We have developed a design support tool based on the proposed technique. By applying our method to development of a basic functionality of a cellular phone, we could decide which functional modules should be implemented as dedicated HW units or on-chip-CPUs' software, and select suitable DSPs and memories with low costs