35 research outputs found

    Implementation of Boolean Logic Functions in Charge Trap Flash for In-Memory Computing

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    A study on the mask of interpolatory symmetric subdivision schemes

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    In the work, we rebuild the masks of well-known interpolatory symmetric subdivision schemes-binary 2n-point interpolatory schemes, the ternary 4-point interpolatory scheme using only the symmetry and the necessary condition for smoothness and the butterfly scheme, and the modified butterfly scheme using the factorization property

    Image deformation using radial basis function interpolation

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    Image deformation technique is widely used in the field of computer animation, image editing, medical imaging, and other applications in 2D and 3D computer graphics. All the algorithms aim to provide simple user interface, most of which need the user to drag the control points, lines or polygon. The deformation process and the final position of the controlling points should be smooth and precise respectively, and it should also run in real-time. This paper provides a simple image deformation method using the radial basis function interpolation in approximation theory. Radial basis function is a very popular and convenient tool for data representation problems. The proposed method using radial basis function is fast and easy to use more than previous deformation methods. Experiments indicate that the algorithm is stable and well performed

    Design and Analysis of Core-Gate Shell-Channel 1T DRAM

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    The work showcases the utility of core-gate shell-channel (CGSC) architecture for one-transistor dynamic random-access memory (1T DRAM). The advantage of gate-all-around (GAA) is that the structure has less variability issue compared with other multi-gate devices. CGSC in GAA helps to achieve a fully-depleted channel and form deeper potential well for effective charge storage. The proposed 1T DRAM cell achieves retention time (T-ret) of similar to 3.5 s at 85 degrees C for a gate length of 100 nm and similar to 5 ms at and 125 degrees C with gate length of 10 nm, even at elevated temperatures. The device demonstrates low power (25.18 nW for write "1") and energy (0.02 fJ for read "0") consumptions for DRAM operations.N
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