A compact butterfly-style silicon photonic-electronic neural chip for hardware-efficient deep learning

The optical neural network (ONN) is a promising hardware platform for next-generation neurocomputing due to its high parallelism, low latency, and low energy consumption. Previous ONN architectures are mainly designed for general matrix multiplication (GEMM), leading to unnecessarily large area cost and high control complexity. Here, we move beyond classical GEMM-based ONNs and propose an optical subspace neural network (OSNN) architecture, which trades the universality of weight representation for lower optical component usage, area cost, and energy consumption. We devise a butterfly-style photonic-electronic neural chip to implement our OSNN with up to 7x fewer trainable optical components compared to GEMM-based ONNs. Additionally, a hardware-aware training framework is provided to minimize the required device programming precision, lessen the chip area, and boost the noise robustness. We experimentally demonstrate the utility of our neural chip in practical image recognition tasks, showing that a measured accuracy of 94.16% can be achieved in hand-written digit recognition tasks with 3-bit weight programming precision.Comment: 17 pages,5 figure

Monolithic and hybrid nanophotonic chips for high-speed and power-efficient optical computing and interconnects

Past decades have witnessed the unprecedented success in very-large scale integration-based electronic computing, as indicated by the Moore’s law. Transistors continue to scale down from micrometer to nanometer and computing cores continue to increase with all the benefits of lower power consumption and higher speed coming naturally until the falter of Moore’s law in recent years as nanofabrication technology approaches its inevitable limit. Remarkable efforts have been made to develop high-speed and power-efficient computing alternatives in this post-Moore’s law era. The exploration of optical computing started as early as ~1970s when integrated electronic computing was just about to take off. The continuous success of electronic computing over decades has not slowed down but instead stimulated the research on optical computing. It is because photonics own unique and fascinating properties such as ultrahigh speed, high bandwidth, and various multiplexing techniques, making it a promising candidate to supersede electronics especially when electronics face unsolvable obstacles. Fortunately, in this post-Moore’s law era, integrated photonics has evolved rapidly with abundant passive and active micrometer-size components available with ultralow power consumption. It enables integrated optical computing to be comparable with transistor-based electronic computing in terms of speed and power. In this dissertation, a new architecture of electronic-photonic computing will be presented, which makes the full use of electronics and photonics to achieve ultrahigh-speed and low-power-consumption computing that are comparable with the state-of-the-art transistors-based electronic computing. This dissertation will cover bottom-to-top discussions, ranging from gates, circuits, to automatic design algorithm, to architecture and entire system. First, it starts with the introduction of electro-optic logic and then the design and analysis of fundamental logic gates and circuits along with the essential components such as electro-optic modulators. Second, an automated logic synthesis algorithm called And-Inverter Graph will be presented, which is capable of designing computing circuits using these fundamental logic gates automatically and efficiently. Third, an electronic-photonic arithmetic logic unit is proposed with an experimental demonstration of 4-bit circuit operating at 20 GHz. Thorough discussion of the performance is also conducted which shows its potential to surpass the state-of-the-art transistors-based computing circuits in terms of speed and power. Forth, a Moore’s law in optical computing is discussed with one promising method called multi-operand logic gates provided. Lastly, architectural considerations of electronic-photonic computing are presented.Electrical and Computer Engineerin

Wavelength-division-multiplexing (WDM)-based integrated electronic–photonic switching network (EPSN) for high-speed data processing and transportation

Integrated photonics offers attractive solutions for realizing combinational logic for high-performance computing. The integrated photonic chips can be further optimized using multiplexing techniques such as wavelength-division multiplexing (WDM). In this paper, we propose a WDM-based electronic–photonic switching network (EPSN) to realize the functions of the binary decoder and the multiplexer, which are fundamental elements in microprocessors for data transportation and processing. We experimentally demonstrate its practicality by implementing a 3–8 (three inputs, eight outputs) switching network operating at 20 Gb/s. Detailed performance analysis and performance enhancement techniques are also given in this paper

Efficient On-Chip Learning for Optical Neural Networks Through Power-Aware Sparse Zeroth-Order Optimization

Optical neural networks (ONNs) have demonstrated record-breaking potential in high-performance neuromorphic computing due to their ultra-high execution speed and low energy consumption. However, current learning protocols fail to provide scalable and efficient solutions to photonic circuit optimization in practical applications. In this work, we propose a novel on-chip learning framework to release the full potential of ONNs for power-efficient in situ training. Instead of deploying implementation-costly back-propagation, we directly optimize the device configurations with computation budgets and power constraints. We are the first to model the ONN on-chip learning as a resource-constrained stochastic noisy zeroth-order optimization problem, and propose a novel mixed-training strategy with two-level sparsity and power-aware dynamic pruning to offer a scalable on-chip training solution in practical ONN deployment. Compared with previous methods, we are the first to optimize over 2,500 optical components on chip. We can achieve much better optimization stability, 3.7x-7.6x higher efficiency, and save >90% power under practical device variations and thermal crosstalk

A Compact Butterfly-Style Silicon Photonic–Electronic Neural Chip for Hardware-Efficient Deep Learning

The optical neural network (ONN) is a promising hardware platform for next-generation neurocomputing due to its high parallelism, low latency, and low energy consumption. Previous ONN architectures are mainly designed for general matrix multiplication (GEMM), leading to unnecessarily large area cost and high control complexity. Here, we move beyond classical GEMM-based ONNs and propose an optical subspace neural network (OSNN) architecture, which trades the universality of weight representation for lower optical component usage, area cost, and energy consumption. We devise a butterfly-style photonic–electronic neural chip to implement our OSNN with up to 7× fewer trainable optical components compared to GEMM-based ONNs. Additionally, a hardware-aware training framework is provided to minimize the required device programming precision, lessen the chip area, and boost the noise robustness. We experimentally demonstrate the utility of our neural chip in practical image recognition tasks, showing that a measured accuracy of 94.16% can be achieved in handwritten digit recognition tasks with 3 bit weight programming precision