1,772 research outputs found

    Run-time power and performance scaling in 28 nm FPGAs

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    Gbit/second lossless data compression hardware

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    This thesis investigates how to improve the performance of lossless data compression hardware as a tool to reduce the cost per bit stored in a computer system or transmitted over a communication network. Lossless data compression allows the exact reconstruction of the original data after decompression. Its deployment in some high-bandwidth applications has been hampered due to performance limitations in the compressing hardware that needs to match the performance of the original system to avoid becoming a bottleneck. Advancing the area of lossless data compression hardware, hence, offers a valid motivation with the potential of doubling the performance of the system that incorporates it with minimum investment. This work starts by presenting an analysis of current compression methods with the objective of identifying the factors that limit performance and also the factors that increase it. [Continues.

    Optimised OpenCL workgroup synthesis for hybrid ARM-FPGA devices

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    Evaluation of Hybrid Run-Time Power Models for the ARM Big.LITTLE Architecture

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    CPCIe:A Compression-enabled PCIe Core for Energy and Performance Optimization

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