Challenge of crystalline IGZO ceramics to silicon LSI - Its application to AI and displays

We found crystalline IGZO ceramics having a layered structure, a crystalline oxide semiconductor called c-axis-aligned crystalline In-Ga-Zn oxide (CAAC-IGZO) in 2009. Recent research has revealed that CAAC-IGZO exhibits a structure in a boundary region between amorphous and crystal structures [1]. We are convinced that CAAC-IGZO is a novel crystalline phase, as shown in Table 1. A field effect transistor (FET) using the crystalline IGZO ceramics with L/W = 0.8μm/100mm exhibits an off leakage current of 6yA/μm (10-24A/μm) at 85°C, which is such a low current that FETs using Si, the dominant semiconductor material, cannot ever achieve [2]. In the display industry, FETs utilizing this feature have been increasingly mounted on panel backplanes and widely adopted in various products such as TVs and smartphones. CAAC-IGZO FETs have a high on/off ratio and thus are being applied also to the field of LSI; a 60nm-node prototype line for mass production started operating [3]. CAAC-IGZO FETs are effective for applications such as FPGA, GPU, and DRAM, and are now being developed to target image processors and artificial intelligence (AI). CAAC-IGZO FETs are known to have mobility that does not deteriorate at high temperatures [5]. Figure 1 shows cutoff frequency (fT) of a CAAC-IGZO FET and a Si FET at varying temperatures. While there is a difference in fT of the Si FET between 27°C and 150°C, a change in fT between different temperature conditions is small in the CAAC-IGZO FET. Moreover, fT of the CAAC-IGZO FET is 33GHz, which is approximately 1/4 that of the Si FET (137GHz). These results demonstrate that the on-state current and field-effect mobility of the CAAC-IGZO FET do not decrease with increasing temperature. Please click Additional Files below to see the full abstract

Invited: Challenge to next-generation VLSI with VFET using oxide semiconductor and 3D structure

on OSLSI by John Wiley & Sons, Inc., in 2017 [1]. OS has attracted such attention that almost 10% of the accepted papers was related to the field at the IEEE International Electron Devices Meeting (IEDM), the world\u27s largest international conference on semiconductor manufacturing, held in December 2022. In the tutorial taught by IBM on the first day of IEEE IEDM 2022, the necessity of vertical field-effect transistors (VFETs) and stacked FETs was anticipated for beyond-1-nm-node semiconductors that are next to the 2- to 3-nm-node semiconductors [2]. A gate-all-around (GAA) structure has been proposed as the new structure in the Si VLSI field. However, we propose a VFET structure that goes a step ahead of the GAA structure and are convinced that a VFET using OS and a 3D structure (stack structure) in which the VFETs are stacked vertically will be the next mainstream. Please download the additional file to see the full abstract

Analysis of IGZO crystalline structure and its stability by first-principles calculations

In-Ga-Zn oxide (IGZO), an oxide semiconductor, has been actively researched as a semiconductor material having features different from those of silicon in recent years [1]. IGZO is used as a transistor material in backplanes of commercially available displays. Transistors including crystalline IGZO have high stability and thus are suitable for mass production [2]. Our previous studies revealed that the selected area diffraction pattern of an IGZO film formed at room temperature by sputtering is a halo pattern, whereas diffraction spots are observed in the diffraction pattern obtained by nanobeam electron diffraction with a probe diameter of 1 nm [3,4]. These results suggest that the IGZO film has rather nanometer-sized crystalline structures than a completely amorphous structure. We named this film “nano-crystalline IGZO (nc-IGZO) film.” Other researchers have reported that the nc-IGZO film has a crystalline-cluster composite structure, according to the analysis results obtained by grazing-incidence X-ray diffraction, anomalous X-ray scattering, and reverse-Monte-Carlo simulation [5]. In this study, an IGZO structure having a minute crystalline region, which was considered to exist in nc-IGZO as a local structure, was created by first-principles calculations and its stability was analyzed. The IGZO model having a crystalline region used in this study was obtained by a melt-quench method in the following manner. Note that the initial structure had a hexagonal-prism crystalline region at the center and an amorphous region (random atomic arrangement) around the crystalline region. The composition ratio was In:Ga:Zn:O = 1:1:1:4 and the density was 6.1 g/cm3. First, for structural relaxation with the crystalline region maintained, the amorphous region was fused in quantum molecular dynamics simulation (3500 K, 6 ps) while the atomic arrangement of the crystalline region was fixed, and the structure was cooled to 500 K at a rate of 500 K/ps and held at 300 K for 5 ps. Finally, the entire structure including the crystalline region was optimized towards the target structure (Fig. 1). An amorphous model was also created for reference. The amorphous model was obtained by quantum molecular dynamics simulation of the entire structure under similar temperature conditions without fixing the atomic arrangement of the crystalline region, followed by structural optimization. The comparison between the two models showed that the total energy of the IGZO model having a crystalline region was lower than that of the amorphous model (not having a crystalline region). This suggests that the crystalline region contributes to structure stabilization. Please click Additional Files below to see the full abstract

Crystallinity of In-Ga-Zn-oxide (IGZO) in CAAC-IGZO vertical FET

Oxide semiconductor field-effect transistors (OSFETs) are actively developed [1]. In particular, there are many reports on a typical oxide semiconductor, In-Ga-Zn oxide (IGZO) [2]. An OSFET is fabricated with a planar structure in many cases; however, a vertical FET (VFET) with a current path perpendicular to a substrate can be fabricated with an area overhead comparable to one trench hole, and is gathering attention [3]. The VFET structure enables OSFETs to be highly integrated, and also allows the resolution of displays to be higher. Please click Download on the upper right corner to see the full abstract

Vertical oxide semiconductor field-effect transistor with extremely low off-state current

Oxide semiconductor field-effect transistors (OSFETs) are actively developed for display applications. An OSFET exhibits a lower off-state current than a silicon FET and enables low-frequency driving. We developed the measurement method and revealed the OSFET exhibits an extremely low off-state current [1]. In addition, we discovered a c-axis aligned crystalline indium-gallium-zinc oxide (CAAC-IGZO) which was unique crystal morphology [2]. A display with a backplane formed using CAAC-IGZO FETs achieves low power consumption owing to idling-stop driving that allows an extremely low refresh rate [3]. Please click Download on the upper right corner to see the full abstract

Embedded DRAM using c-axis-aligned crystalline In-Ga-Zn oxide FET with 1.8V-power-supply voltage

An embedded memory using c-axis aligned crystalline In-Ga-Zn oxide (CAAC-IGZO) FETs with an extremely low off-state current on the order of yoctoamperes (yA) (yocto- is a metric prefix denoting a factor of 10-24) is known as a potential next-generation memory [1][2]. A dynamic oxide semiconductor RAM (DOSRAM), where each memory cell is composed of one CAAC-IGZO FET and one capacitor, enables long data retention and long interval of refresh operations with an advantage of extremely low off-state current of the CAAC-IGZO FET. However, negative backgate voltage (Vbg) and word-line driving voltages of 0/3.3 V (VSSL/VDDH) had been required for an access transistor of the memory cell to satisfy high on-state current and low off-state current. This work shows that DOSRAM operates with 1.8 V-power supply voltage by using a novel driving method. Figure 1 shows Vg-Id performance of a CAAC-IGZO FET used as a cell transistor. The threshold voltage (Vth) of the CAAC-IGZO FET is controlled by changing a level of Vbg, whereas Vth of the Si FET is controlled by channel doping. Figure 2 shows a block diagram of a prototyped DOSRAM. The refresh rate in DOSRAM mainly depends on the leakage current of cell transistors. To reduce the refresh rate to once an hour, the off-state current of the cell transistors on a non-selected word line needs to be reduced to 200 zeptoamperes (zA) per FET (zepto- is a metric prefix denoting a factor of 10-21) or lower at 85C. The required Vbg is -7.0 V to achieve such an off-state current at Vg 0 V, for example. To obtain approx. 100 MHz-driving frequency, the required on-state current is at least several microamperes. The voltage level difference in the word line, VDDH VSSL, is a factor that determines the on-state current, and in this work is fixed to 3.3 V so that the combination of Vbg and the word line voltage is optimized. The application of negative voltage to the word line enables the leakage current of the cell transistor to be maintained low even when Vbg is increased. For example, whereas the existing driving method meets the above off-state current value with Vbg -7.0 V and the VSSL 0 V, the novel driving method meets the value with Vbg 0 V and VSSL -1.5 V. In the novel driving method, VDDH 1.8 V. There has been a report of a reduction in leakage current of a memory cell by application of negative voltage to a top gate in DRAM using Si CMOS [3]. In contrast to it, DOSRAM including CAAC-IGZO FETs with L 60 nm has a leakage current of 200 zA or lower, which is 7-digit lower than that of the DRAM using Si CMOS, and enables longer data retention. The evaluation results of the prototyped DOSRAM verify that a reduction in power-supply voltage from 3.3 V to 1.8 V is possible in terms of operation and data retention. This suggests a highly compatible and efficient configuration of an embedded DRAM and a logic circuit where signals can be transmitted with low VDD. References [1] S. H. Wu, et al., IEEE Symp. VLSI Tech., pp. 166-167, 2017. [2] T. Ishizu, et al., IEEE Symp. VLSI Cir., pp. 162-163, 2017. [3] F. Hamzaoglu et al., IEEE Journal of Solid-State Circuits, vol. 50, no. 1, pp. 150-157, Jan. 2015

Low-power display system enabled by combining oxide semiconductor and neural network technologies

An oxide semiconductor (OS)-based field effect transistor (OSFET) exhibits the advantage of having an extremely low off-state current; moreover, the OSFET displays an off-state current that is ten orders of magnitude lower than that of a CMOS-FET [1]. Recently, numerous applications that harness this feature have been reported [2]. For instance, charge leakage from a data retention node of a pixel significantly decreases when the display incorporates OSFETs in its pixel circuit (OS display) [3, 4]. This minimizes degradation in the image quality when the displayed image is static despite using lower refresh rates. Consequently, the consumed power of the display driver circuit can be reduced by a large margin. This driving method is termed idling stop (IDS) driving. The OSFET’s low-leakage can also effectively enable a type of ULSICs that we term OS-large-scale integrated circuits (OSLSI) [5, 6]. Please click Additional Files below to see the full abstract