Platinum and gold nanostructures on silicon via a self-assembled template

Parallel arrays of self-assembled rare earth disilicides (erbium and dysprosium) nanowires were grown on Si(001) substrates with nanowire width between 3-10 nm and used as a template for fabricating noble metal (platinum and gold) nanostructure arrays. Submonolayer coverage of platinum and gold were deposited on the nanowire/Si(001) surface post rare earth disilicide growth. Scanning tunneling microscopy and reactive ion etching showed that platinum and gold preferentially deposited on the nanowire surface versus the Si surface. Reactive ion etching of erbium disilicide nanowires with and without platinum on the surface demonstrated that platinum acted as a more resistant etch mask than erbium disilicide. By varying the platinum coverage on the surface we demonstrate the ability to select arrays of nanowire or nanocrystal arrays as a function of platinum coverage

Memristive switching mechanism for matal/oxide/metal nano-devices

Nanoscale metal/oxide/metal switches have the potential to transform the market for nonvolatile memory and could lead to novel forms of computing. However, progress has been delayed by difficulties in understanding and controlling the coupled electronic and ionic phenomena that dominate the behaviour of nanoscale oxide devices. An analytic theory of the ‘memristor’ (memory-resistor) was first developed from fundamental symmetry arguments in 1971, and we recently showed that memristor behaviour can naturally explain such coupled electron –ion dynamics. Here we provide experimental evidence to support this general model of memristive electrical switching in oxide systems. We have built micro- and nanoscale TiO2 junction devices with platinum electrodes that exhibit fast bipolar nonvolatile switching. We demonstrate that switching involves changes to the electronic barrier at the Pt/TiO2 interface due to the drift of positively charged oxygen vacancies under an applied electric field. Vacancy drift towards the interface creates conducting channels that shunt, or short-circuit, the electronic barrier to switch ON. The drift of vacancies away from the interface annilihilates such channels, recovering the electronic barrier to switch OFF. Using this model we have built TiO2 crosspoints with engineered oxygen vacancy profiles that predictively control the switching polarity and conductance

Regular Arrays of Monodisperse Platinum/Erbium Disilicide Core−Shell Nanowires and Nanoparticles on Si(001) via a Self-Assembled Template

We have developed a process for fabricating monodisperse noble metal/rare earth disilicide core-shell nanoparticles and nanowires in regular arrays on Si(001) with a density of 5 x 10(10) / cm2, and over areas > 1 mm2. Pt deposited via physical vapor deposition on a self-assembled rare earth disilicide nanowire template combined with reactive ion etching produces arrays of nanostructures. SEM images demonstrate the ability to select nanowires or nanoparticles as a function of Pt coverage. Statistical analysis of images of Pt nanoparticle arrays yield a mean feature size of 8 nm with a size variation of +/- 0.9 nm and interparticle spacing of approximately 15 nm

A hybrid nanomemristor/transistor logic circuit capable of self-programming

Memristor crossbars were fabricated at 40 nm half-pitch, using nanoimprint lithography on the same substrate with Si metal-oxide-semiconductor field effect transistor (MOS FET) arrays to form fully integrated hybrid memory resistor (memristor)/transistor circuits. The digitally configured memristor crossbars were used to perform logic functions, to serve as a routing fabric for interconnecting the FETs and as the target for storing information. As an illustrative demonstration, the compound Boolean logic operation (A AND B) OR (C AND D) was performed with kilohertz frequency inputs, using resistor-based logic in a memristor crossbar with FET inverter/amplifier outputs. By routing the output signal of a logic operation back onto a target memristor inside the array, the crossbar was conditionally configured by setting the state of a nonvolatile switch. Such conditional programming illuminates the way for a variety of self-programmed logic arrays, and for electronic synaptic computing

Ensembles of indium phosphide nanowires: physical properties and functional devices integrated on non-single crystal platforms

A new route to grow an ensemble of indium phosphide single-crystal semiconductor nanowires is described. Unlike conventional epitaxial growth of single-crystal semiconductor films, the proposed route for growing semiconductor nanowires does not require a single-crystal semiconductor substrate. In the proposed route, instead of using single-crystal semiconductor substrates that are characterized by their long-range atomic ordering, a template layer that possesses short-range atomic ordering prepared on a non-single-crystal substrate is employed. On the template layer, epitaxial information associated with its short-range atomic ordering is available within an area that is comparable to that of a nanowire root. Thus the template layer locally provides epitaxial information required for the growth of semiconductor nanowires. In the particular demonstration described in this paper, hydrogenated silicon was used as a template layer for epitaxial growth of indium phosphide nanowires. The indium phosphide nanowires grown on the hydrogenerated silicon template layer were found to be single crystal and optically active. Simple photoconductors and pin-diodes were fabricated and tested with the view towards various optoelectronic device applications where group III–V compound semiconductors are functionally integrated onto non-single-crystal platforms

Ensembles of indium phosphide nanowires: physical properties and functional devices integrated on non-single crystal platforms

A new route to grow an ensemble of indium phosphide single-crystal semiconductor nanowires is described. Unlike conventional epitaxial growth of single-crystal semiconductor films, the proposed route for growing semiconductor nanowires does not require a single-crystal semiconductor substrate. In the proposed route, instead of using single-crystal semiconductor substrates that are characterized by their long-range atomic ordering, a template layer that possesses short-range atomic ordering prepared on a non-single-crystal substrate is employed. On the template layer, epitaxial information associated with its short-range atomic ordering is available within an area that is comparable to that of a nanowire root. Thus the template layer locally provides epitaxial information required for the growth of semiconductor nanowires. In the particular demonstration described in this paper, hydrogenated silicon was used as a template layer for epitaxial growth of indium phosphide nanowires. The indium phosphide nanowires grown on the hydrogenerated silicon template layer were found to be single crystal and optically active. Simple photoconductors and pin-diodes were fabricated and tested with the view towards various optoelectronic device applications where group III–V compound semiconductors are functionally integrated onto non-single-crystal platforms

A 14-ps Full Width at Half Maximum High-Speed Photoconductor Fabricated with Intersecting InP Nanowires on an Amorphous Surface

We demonstrate a high-speed polarization-insensitive photoconductor based on intersecting InP nanowires synthesized between a pair of hydrogenated silicon electrodes deposited on amorphous SiO2 surfaces prepared on silicon substrates. A 14-ps full width at half maximum de-embedded impulse response is measured, which is the fastest reported response for a photodetector fabricated using nanowires. The high-speed electrical signal measurements from the photoconductor are performed by an integrated coplanar waveguide transmission line. The demonstrated ability to grow intersecting InP nanowires on hydrogenated microcrystalline Si surfaces will facilitate the construction of ultra-fast photodetectors on a wide range of substrates