Scalable data concentrator with baseline interconnection network for triggerless data acquisition systems

Triggerless Data Acquisition Systems (DAQs) require transmitting the data stream from multiple links to the processing node. The short input data words must be concentrated and packed into the longer bit vectors the output interface (e.g. PCI Express) uses. In that process, the unneeded data must be eliminated, and a dense stream of useful DAQ data must be created. Additionally, the time order of the data should be preserved. This paper presents a new solution using the Baseline Network with Reversed Outputs (BNRO)for high-speed data routing. A thorough analysis of the network operation enabled increased scalability compared to the previously published concentrator based on 8x8 network. The presented solution may be scaled by adding additional layers to the BNRO network while minimizing resource consumption. Simulations were done for 4 and 5 layers (16 and 32 inputs). The FPGA synthesis has been performed for 16 inputs. The pipeline registers may be added in each network independently, shortening the critical path and increasing the maximum acceptable clock frequency

SMX and front-end board tester for CBM readout chain

The STS-MUCH-XYTER (SMX) chip is a front-end ASIC dedicated to the readout of Silicon Tracking System (STS) and Muon Chamber (MUCH) detectors in the Compressed Baryonic Matter (CBM) experiment. The production of the ASIC and the front-end boards based on it is just being started and requires thorough testing to assure quality. The paper describes the SMX tester based on a standard commercial Artix-7 FPGA module with an additional simple baseboard. In the standalone configuration, the tester is controlled via IPbus and enables full functional testing of connected SMX, front-end board (FEB), or a full detector module. The software written in Python may easily be integrated with higher-level testing software

Synchronization methods for the PAC RPC trigger system in the CMS experiment

The PAC (pattern comparator) is a dedicated muon trigger for the CMS (Compact Muon Solenoid) experiment at the LHC (Large Hadron Collider). The PAC trigger processes signals provided by RPC (resistive plate chambers), a part of the CMS muon system. The goal of the PAC RPC trigger is to identify muons, measure their transverse momenta and select the best muon candidates for each proton bunch collision occurring every 25 ns. To perform this task it is necessary to deliver the information concerning each bunch crossing from many RPC chambers to the trigger logic at the same moment. Since the CMS detector is large (the muon hits are spread over 40 ns), and the data are transmitted through thousands of channels, special techniques are needed to assure proper synchronization of the data. In this paper methods developed for the RPC signal synchronization and synchronous transmission are presented. The methods were tested during the MTCC (magnet test and cosmic challenge). The performance of the synchronization methods is illustrated by the results of the tests

Control and Diagnostics System Generator for Complex FPGA-Based Measurement Systems

FPGA-based data acquisition and processing systems play an important role in modern high-speed, multichannel measurement systems, especially in High-Energy and Plasma Physics. Such FPGA-based systems require an extended control and diagnostics part corresponding to the complexity of the controlled system. Managing the complex structure of registers while keeping the tight coupling between hardware and software is a tedious and potentially error-prone process. Various existing solutions aimed at helping that task do not perfectly match all specific requirements of that application area. The paper presents a new solution based on the XML system description, facilitating the automated generation of the control system’s HDL code and software components and enabling easy integration with the control software. The emphasis is put on reusability, ease of maintenance in the case of system modification, easy detection of mistakes, and the possibility of use in modern FPGAs. The presented system has been successfully used in data acquisition and preprocessing projects in high-energy physics experiments. It enables easy creation and modification of the control system definition and convenient access to the control and diagnostic blocks. The presented system is an open-source solution and may be adopted by the user for particular needs

Object oriented hardware-software test bench for OMTF diagnosis

In this paper the object oriented hardware-software model and its sample implementation of diagnostics for the Overlap Muon Track Finder trigger for the CMS experiment in CERN is described. It presents realization of test-bench for control and diagnosis class of multichannel, distributed measurement systems based on FPGA chips. The test-bench fulfills requirements for system’s rapid changes, configurability and efficiency. This ability is very significant and desirable by expanded electronic systems. The solution described is a software model based on a method of address space management called the Component Internal Interface (CII). Establishment of stable link between hardware and software, as a purpose of designed and realized programming environment, is presented. The test-bench implementation and example of OMTF algorithm test is presented.© (2015) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only

OMTF firmware overview

This paper describes firmware architecture of a new part of muon trigger system of the CMS detector – one of four detectors installed along LHC accelerator in CERN. Overlap Muon Track Finder (OMTF) is a new trigger subsystem designed to work in difficult barrel-endcap region of CMS detector. OMTF is designed to receive data from different detector types and process it to select 3 best muon candidates. These muon candidates are then forwarded to Global Muon Trigger (GMT). Performance requirements demanded usage of custom designed hardware. All the data reception and processing takes part in modern, large FPGA device. The IPBus module allows easy firmware control and diagnostics via Ethernet connection.© (2015) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only