Thin SIMOX SOI material for half-micron CMOS

\u3cp\u3eThe properties of half-micron CMOS devices fabricated on thin film SIMOX SOI with different material quality will be presented. The gate oxide quality, diode leakage current and breakdown voltage of transistors will be shown. The influence of LDD dope and TiSi\u3csub\u3e2\u3c/sub\u3esalicide on the parasitic bipolar transistor breakdown is presented. Temperature measurements on SOI and bulk transistors are presented which show an increased heating effect for thin film SOI transistors.\u3c/p\u3

An experimental investigation on weak localisation, spin-orbit and interaction effects in thin bismuth films

\u3cp\u3eThe authors have measured the low-temperature (0.02<T<10K) electronic conductivity, magnetoresistance and Hall constant in thin (20-200 nm) bismuth films. The aim was to study weak localisation, spin-orbit and electron-electron interaction mechanisms in this well suited material. The authors compared their data with theories of Hikami et al. (1980) and Altshuler et al. (1980, 1981). It was found that their data must be interpreted in terms of two independent mechanisms, i.e. electron-electron interaction and spin-orbit scattering. Weak localisation is completely suppressed by the strong spin-orbit scattering in this material.\u3c/p\u3

Comparison of buried and surface channel PMOS devices for low voltage 0.5 μm CMOS

\u3cp\u3eA low voltage option in a 0.5 μm CMOS process technology is described. The key technological issue is the threshold voltage and sub-threshold leakage characteristics of the PMOS devices. The device properties of the n\u3csup\u3e+\u3c/sup\u3e-gate buried channel devices will be compared with the corresponding p\u3csup\u3e+\u3c/sup\u3e-gate surface channel devices. For power supply voltages down to 0.9 V the surface channel PMOS devices revealed superior transistor performance. Furthermore, the off-current characteristics are superior to the n\u3csup\u3e+\u3c/sup\u3e-gate buried channel devices. A minimum threshold voltage of -0.35 V of the 0.45 μm physical gate length PMOS transistor with less then 0.1 nA/μm leakage current was realised in a 0.5 μm CMOS process.\u3c/p\u3

A simple model for quantisation effects in heavily-doped silicon MOSFETs at inversion conditions

\u3cp\u3eThe transistor parameters of state-of-the-art MOSFETs are affected by quantisation effects of the carrier motion in the inversion channel. To account for these effects in classical device stimulators, we show that a better modeling of the silicon bandgap at inversion conditions is ifE\u3csub\u3eg\u3c/sub\u3e\u3csup\u3eQM\u3c/sup\u3e = E\u3csub\u3eg\u3c/sub\u3e\u3csup\u3eCONV\u3c/sup\u3e + 13 9Δε{lunate} in which Δε{lunate} is the position of the first energy level with respect to the bottom of the conduction band. The improved modeling of the bandgap leads to a new model for the intrinsic carrier concentration n\u3csub\u3ei\u3c/sub\u3e. The model for n\u3csub\u3ei\u3c/sub\u3e has been tested against measurements and against self-consistent QM calculations. Excellent agreement is obtained.\u3c/p\u3

Towards modelling of patient-ventilator interactions using model based methods

Mechanical ventilation is an important life-saving intervention on the ICU. Lung-protective ventilation techniques such as pressure support ventilation (PSV) are used frequently in the ICU. However, asynchronies, poor patient-ventilator interactions during PSV, are shown to be harmful and are linked with increased lung injury and mortality. There is a need for automatic detection and classification of asynchronies for clinical studies, algorithm development and for real time clinical decision support for smart ventilation technologies. So far, reasonable results of detection of asynchronies have been obtained, but classification is still a challenge. In this work, we generate training and classification waveforms for our machine learning study using a patient-ventilator simulation model. From these models the flow, pressure and volume waveforms can be created for different types of parameter settings. Note that the type of asynchrony and timing of the patient effort are known

Dependency of dishing on polish time and slurry chemistry in Cu CMP

\u3cp\u3eIn this paper the influences of slurry chemistry and thickness of the copper layer on dishing will be discussed. The dishing is studied for different patterns and variable polishing times. We found that the concentration of the oxidizer and the thickness of copper layer have a strong impact on dishing. The larger Cu features develop dishing at a higher rate than smaller structures during overpolishing. The experimental results lead to the following hypothesis for the Cu removal and surface passivation. The oxidizer (H\u3csub\u3e2\u3c/sub\u3eO\u3csub\u3e2\u3c/sub\u3e) reacts with Cu in an acidic slurry (pH 4) and Cu\u3csup\u3e2+\u3c/sup\u3e ions are formed. The anions of the carboxylic acid react with Cu\u3csup\u3e2+\u3c/sup\u3e ions and form an insoluble salt (R(COO)\u3csub\u3e2\u3c/sub\u3eCu) which passivates the surface. This passivation layer is removed in protruding areas by mechanical abrasion. Once removed from the surface, the `metallic soap' particles are swept away by the turbulent motion in the slurry .\u3c/p\u3

Chemical mechanical polishing for planarisation of advanced IC processes

\u3cp\u3eAn CMP process will be presented which is optimised for low layout sensitivity and good uniformity. The best results were obtained by using a stack of two polishing cloths, instead of a single cloth. This results in a better planarisation capability while improving the uniformity compared to a single hard polishing cloth. The feasibility of the novel CMP process was demonstrated on a 64k SRAM.\u3c/p\u3

Positive oxide-charge generation during 0.25 µm PMOSFET hot-carrier degradation

\u3cp\u3eA new hot-carrier degradation mechanism becomes important in 0.25 µm PMOSFET's. Hot-hole injection generates positive oxide charge near the drain. We determine the time dependence and the oxide-thickness dependence and we show a considerable enhancement of this degradation mechanism for nitrided gate oxides. For many bias conditions and many geometries, the time dependence of PMOSFET degradation can be successfully described by a summation of the time dependences of three separate degradation mechanisms: generation of interface states, negative oxide charge and positive oxide charge.\u3c/p\u3

Conduction and trapping mechanisms in SiO\u3csub\u3e2\u3c/sub\u3e films grown near room temperature by multipolar electron cyclotron resonance plasma enhanced chemical vapor deposition

\u3cp\u3eThe electric conduction and trapping mechanisms of silicon dioxide layers deposited using an electron cyclotron resonance plasma source were studied. It was found that the Fowler-Nordheim tunneling was the dominant conduction mechanism in the SiO\u3csub\u3e2\u3c/sub\u3e films obtained with low silane flow and at low pressure. The current at low biases was observed to be highly dependent on temperature for layers deposited with higher silane flows and higher pressures. It was confirmed using constant current stress measurements that low silane flow and low total pressure are suitable deposition conditions for obtaining a film comparable to thermally grown oxides.\u3c/p\u3

Novel method of producing ultrasmall platinum silicide gate electrodes

\u3cp\u3eA novel method has been developed for producing platinum silicide gate electrodes with submicron width. A lateral chemical reaction of platinum with polycrystalline silicon at a step edge was used. The width of the wire is determined by the thickness of a sputtered metal layer. Wires with width between 35 and 300 nm have been produced. The method has been used for making long-channel field-effect transistors with good device properties. Some preliminary results of the study of the low-temperature electrical transport properties of inversion layers with width of 0.12 μm are reported.\u3c/p\u3