Comparison of buried and surface channel PMOS devices for low voltage 0.5 μm CMOS

Abstract

\u3cp\u3eA low voltage option in a 0.5 μm CMOS process technology is described. The key technological issue is the threshold voltage and sub-threshold leakage characteristics of the PMOS devices. The device properties of the n\u3csup\u3e+\u3c/sup\u3e-gate buried channel devices will be compared with the corresponding p\u3csup\u3e+\u3c/sup\u3e-gate surface channel devices. For power supply voltages down to 0.9 V the surface channel PMOS devices revealed superior transistor performance. Furthermore, the off-current characteristics are superior to the n\u3csup\u3e+\u3c/sup\u3e-gate buried channel devices. A minimum threshold voltage of -0.35 V of the 0.45 μm physical gate length PMOS transistor with less then 0.1 nA/μm leakage current was realised in a 0.5 μm CMOS process.\u3c/p\u3