Ion Implanted Phosphorous for 4H-SiC VDMOSFETs Source Regions: Effect of the Post Implantation Annealing Time

Van der Pauw devices have been fabricated by double ion implantation processes, namely P+ and Al+ co-implantation. Similarly to the source area in a SiC VD-MOSFET, a 5 × 1018 cm-3 P plateau is formed on the top of a buried 3 × 1018 cm-3 Al distribution for electrical isolation from the n- epilayer. The post implantation annealing temperature was 1600 °C. Annealing times equal to 30 min and 300 min have been compared. The increase of the annealing time produces both an increase of electron density as well as electron mobility. For comparison a HPSI 4H-SiC wafer, 1×1020 cm-3 P+ ion implanted and 1700 °C annealed for 30 min was also characterized.ISSN:0255-5476ISSN:1662-975

Preconception Health Knowledge among Undergraduate Women

Preconception health is a woman’s health before she becomes pregnant. It means knowing and understanding how preexisting health conditions and risk factors could affect a woman or her unborn child if she becomes pregnant (Office on Women’s Health, 2010). This study examined undergraduate students’ knowledge of recommended preconception health practices. A paper survey was distributed to general education classes in health, sociology, and family consumer science. This 33-item survey assessed demographics, barriers to practicing recommended preconception health behaviors, and knowledge of preconception health practices. Analyses included frequencies, independent t-test, and ANOVA. Respondents had a mean score of 42.85 (2.68) on the knowledge section of the survey; indicating that respondents had a high level of knowledge regarding preconception health practices and information. Respondents’ knowledge scores were statistically correlated with their preconception health practices and behaviors (r=.176, p=.000). As knowledge scores increased, preconception health practice and behaviors scores also increased. When analyzing participants’ current health behaviors as they relate to preconception health, it was found that most students are engaging in healthy behaviors

Low-Energy Muons as a Tool for a Depth-Resolved Analysis of the SiO2/4H-SiC Interface

In this work, the potential of muon spin rotation (μSR) with low-energy muons (LE-μ) for the investigation of oxidation-induced defects at the SiO2/4H-SiC interface is explored. By using implantation energies for the muons in the keV range and comparing the fractions of muonium in different regions, the depth distribution of defects in the first 200 nm of the target material can be resolved. Defect profiles of interfaces with either deposited or thermally grown SiO2 layers on 4H-SiC are compared. The results show an increased number of defects in the case of a thermal oxide, both on the oxide and on the SiC side of the interface, with a spatial extension of a few tens of nm.ISSN:0255-5476ISSN:1662-975

Interaction of low-energy muons with defect profiles in proton-irradiated Si and 4H -SiC

ISSN:1098-0121ISSN:0163-1829ISSN:1550-235XISSN:0556-2805ISSN:2469-9969ISSN:1095-379

4H-SiC Power VDMOSFET Manufacturing Utilizing POCl3 Post Oxidation Annealing

A novel POCl3 post-oxidation annealing recipe was developed. The interface trap density (Dit) is extracted by the C-ΨS method close to conduction band edge. The performance of the POCl3-treated oxide has been analyzed based on current density-electric field (J-E) measurements. A comprehensive and practical 4H-SiC power VDMOSFET manufacturing traveler has been designed. The power MOSFET that was fabricated based on this traveler exhibits less than half of the on-resistance and shows improved interface characteristics compared to a similarly designed commercial power MOSFET.ISSN:0255-5476ISSN:1662-975

Sensitivity of Dit extraction at the SiO2/SiC interface using quasi-static capacitance-voltage measurements

In this work, we compare different quasi-static capacitance-voltage measurement systems by analyzing 4H-SiC n-type MOS capacitors and studying the influence of systematic errors when extracting the interface trap density (Dit). We show that the extracted Dit strongly depends on the calculation of the surface potential due to variations of the integration constant �. In addition, the ramp-rate during the quasi-static measurement is identified as a sensitive measurement parameter whose noise level is amplified in the Dit extraction.ISSN:0255-5476ISSN:1662-975

Fast Defect Mapping at the SiO₂/ SiC Interface Using Confocal Photoluminescence

Electrically active defects at the SiO2/SiC interface can have detrimental effects on the device performance of SiC MOSFETs. Capacitance-or conductance-based analysis techniques are commonly used to extract the density of interface defects, despite having the disadvantage of requiring dedicated test structures for the analysis. Here, we discuss confocal sub-bandgap photoluminescence (PL) microscopy as a fast and reliable alternative to conventional electrical characterization techniques. For this purpose, the quality of the SiO2/SiC interface after post-oxidation annealing in N2O is studied both by confocal imaging as well as by the high-low and C-Ψ capacitance technique. We find excellent agreement between the optical and electrical analysis and observe a significant increase of the interface defect density for annealing temperatures below 1050 °C.ISSN:0255-5476ISSN:1662-975

Defect Profiling of Oxide-Semiconductor Interfaces Using Low-Energy Muons

Muon spin rotation with low-energy muons (LE-& mu;SR) is a powerful nuclear method where electrical and magnetic properties of surface-near regions and thin films can be studied on a length scale of & AP;200 nm. This study shows the potential of utilizing low-energy muons for a depth-resolved characterization of oxide-semiconductor interfaces, i.e., for silicon (Si) and silicon carbide (4H-SiC). The performance of semiconductor devices relies heavily on the quality of the oxide-semiconductor interface; thus, investigation of defects present in this region is crucial to improve the technology. Silicon dioxide (SiO2) deposited by plasma-enhanced chemical vapor deposition (PECVD) and grown by thermal oxidation of the SiO2-semiconductor interface are compared with respect to interface and defect formation. The nanometer depth resolution of LE-& mu;SR allows for a clear distinction between the oxide and semiconductor layers, while also quantifying the extension of structural changes caused by the oxidation of both Si and SiC. The results demonstrate that LE-& mu;SR can reveal unprecedented details on the structural and electronic properties of the thermally oxidized SiO2-semiconductor interface.ISSN:2196-735

Analysis of Thin Thermal Oxides on (0001) SiC Epitaxial Layers

In this study, electrical properties of MOS capacitors with varying oxide thicknesses have been investigated. The oxide growth was performed at 1050 °C without any further post-oxidation annealing steps resulting in oxide thicknesses between 2 nm and 32 nm. Capacitance-Voltage measurements revealed a decreasing density of interface defects for increasing oxide thickness suggesting a deterioration of the interface at the initial stage of the growth.ISSN:0255-5476ISSN:1662-975

Phosphorous and Aluminum Implantation for MOSFET Manufacturing: Revisiting Implantation Dose Rate and Subsequent Surface Morphology

In this work, we study the impact of the dose rate on the electrical properties of aluminum (p-body, p+-body-contact) and phosphorous (n-source/drain) implanted 4H-SiC. We find no significant differences for dose rates ranging from 1×1011 cm-2s-1 to 2−7×1012 cm-2s-1. AFM scans across implanted and non-implanted regions after thermal oxidation and subsequent oxide etching reveal a clear dependence of the oxidation rate on the conduction type and doping concentration. In addition, we observe an increasing (decreasing) oxidation rate for increasing doping concentrations of the n-type (p-type) ion implanted areas.ISSN:0255-5476ISSN:1662-975