Identification of protein-coding sequences using the hybridization of 18S rRNA and mRNA during translation

We introduce a new approach in this article to distinguish protein-coding sequences from non-coding sequences utilizing a period-3, free energy signal that arises from the interactions of the 3′-terminal nucleotides of the 18S rRNA with mRNA. We extracted the special features of the amplitude and the phase of the period-3 signal in protein-coding regions, which is not found in non-coding regions, and used them to distinguish protein-coding sequences from non-coding sequences. We tested on all the experimental genes from Saccharomyces cerevisiae and Schizosaccharomyces pombe. The identification was consistent with the corresponding information from GenBank, and produced better performance compared to existing methods that use a period-3 signal. The primary tests on some fly, mouse and human genes suggests that our method is applicable to higher eukaryotic genes. The tests on pseudogenes indicated that most pseudogenes have no period-3 signal. Some exploration of the 3′-tail of 18S rRNA and pattern analysis of protein-coding sequences supported further our assumption that the 3′-tail of 18S rRNA has a role of synchronization throughout translation elongation process. This, in turn, can be utilized for the identification of protein-coding sequences

A Methodology for Hardware Design and Verification of Architectures for Channel Equalization

tures for Channel Equalization. (Under the guidance and direction of Dr. Winser E. Alexan-der.) Hardware implementing wireless applications in today’s cellular systems has stringent requirements such as high speed, flexibility, and low power dissipation resulting in complex systems. These require-ments have led to the development of systems on a single chip. Although this development promises a variety of design advantages, designers are facing new design difficulties and challenges while design-ing these complex systems. Some of the design difficulties and challenges presented by the traditional design flow, in designing these complex systems, are increase in the simulation time, increase in the verification effort required, increase in the time to market, difficulty in exploring the design space, and increase in the productivity gap. In this research work, we introduce a new design flow that starts at the system level. The design flow, called the system-level design flow, promises to reduce the difficulty in exploring the design space, to reduce the simulation times, to reduce the verification and debugging time, to allow the definition of both hardware and software components of a design, and to allow defining the system at a high level of abstraction. To validate our design flow and its advantages, we consider a subsystem for a Wireless Communication System called a “Multiple Input Multiple Output ” (MIMO) wireless communication system for analysis. We consider the designs of channel equalization architectures for the MIMO wire-less communication system. We consider algorithms such as least mean square and iterative conjugate gradient algorithms for implementing channel equalization. We design the algorithms using SystemC and Verilog. We consider the use of SystemVerilog to interface SystemC to the Verilog environment

Methodology for Analyzing Complex Algorithms for Small Satellites

From the view point of an electrical engineer, one of the main challenges in the field of space science is the mapping of complex control algorithms onto appropriate hardware architectures. There is a wide knowledge gap between the team which de-signs these algorithms and the team which implements the algorithms. There is a variety of hardware architectures available commercially onto which the algorithms can be mapped. There also exist different design tools which can be used to perform the implementation of these complex algorithms on appropriate hardware architec-tures. With the availability of a large suite of architectures and design tools, the design engineer often gets puzzled in selecting the correct architecture and tools to perform the implementation of the algorithm in an optimal manner. This thesis presents a methodology for analyzing complex algorithms for small satellite applications. The proposed methodology provides a step by step process of analyzing an algorithm for converting its Platform Independent Model (PIM) into a Platform Specific Model (PSM). It assumes that the algorithm has been designed in Simulink from Mathworks, which is the design tool of choice for aerospace system engineers engineers. After this, the methodology descibes the detailed process of performing complexity analysis of the algorithm, which leads to identification of the accelerator components. The next step explains the process of software and hardware implementation of the accelerator components. After this, the software and hardware implementations are compared on the basis of Speed of Execution, Power Dissipation and Development Time. The results are analyzed to make a decision regarding the implementation of the algorithm. The proposed methodology is validated by applying it to the Atttitude Determi-nation and Control algorithm designed for attitude control of small satellites

Interval Arithmetic Logic Unit for DSP and Control Applications

William W. Edmonson). There are many applications in the field of digital signal processing (DSP) and controls that require the user to know how various numerical errors (uncertainty) affect the result. Interval Arithmetic (IA) eliminates this uncertainty by replacing non-interval values with intervals. Since most DSPs operate in real time environ-ments, fast processors are needed. The goal is to develop a platform in which interval arithmetic operations are performed at the same computational speed as present day signal processors. This thesis proposes a design for an interval based arithmetic logic unit (I-ALU) whose computational time for implementing interval arithmetic operations is equiv-alent to many digital signal processors. Many DSP and control applications require a small subset of arithmetic operations that must be computed efficiently. This de-sign has two independent modules operating in parallel to calculate the lower bound and upper bound of the output interval. The functional unit of the ALU performs the basic fixed-point interval arithmetic operations of addition, subtraction, multi-plication and the interval set operations of union and intersection. In addition, the ALU is optimized to perform dot products through the multiply-accumulate instruc-tion. Division is not implemented on digital signal processors traditionally unless computed with a shift operation. In this design, division by shifting is implemented. One of the prime design goals is to maximize the throughput of the ALU for an optimum value of area. Pipelining is implemented to achieve this design goal. Power dissipation analysis of different ALU architectures is done. Since it required to obtain maximum throughput for the least power dissipation, throughput per unit power dissipation is used as the most critical performance metric. This thesis studies several architectures for the ALU and concludes with the one with the highest performance amongst the ones which are studied

Translation Initiation of Escherichia coli K-12

tors for the Translation Initiation of Escherichia coli K-12. (Under the direction o