41 research outputs found

    Scanning Microwave Microscopy of Aluminum CMOS Interconnect Lines Buried in Oxide and Water

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    Using a scanning microwave microscope, we imaged in water aluminum interconnect lines buried in aluminum and silicon oxides fabricated through a state-of-the-art 0.13 um SiGe BiCMOS process. The results were compared with that obtained by using atomic force microscopy both in air and water. It was found the images in water was degraded by only approximately 60% from that in air.Comment: 3 pages, 5 figures, conferenc

    Development and mechanical modeling of Si1-XGex/Si MQW based uncooled microbolometers in a 130 nm BiCMOS

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    This paper presents the development of process integration and mechanical modeling of a Si1-xGex/Si MQW based uncooled micro-bolometer. The recent progress on layer transfer based integration scheme of Si1-xGex/Si based micro-bolometer into a 130 nm BiCMOS process is presented. The two important parts of the process integration, namely the layer-transfer and stress compensation of the arms are studied. The initial successful results on layer transfer and the FEM modeling for the stress compensation of the thin and narrow arms of the bolometer is presented. Finally, the developed FEM model is compared with the fabricated cantilevers. The results show that the developed FEM model has a very good matching with the experimental results; thus very convenient to use for the FEM modeling of the full bolometer structure

    Filtres SIW en technologie silicium pour applications THz.

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    National audienceCes travaux présentent la mise en oeuvre de filtres en guide d'onde intégré (SIW) pour des applications en bande D (140 GHz) et THz (280 GHz et 400 GHz). Les filtres sont développés sur interposer silicium haute résistivité en utilisant la technologie proposée par IHP. Les filtres présentent des bandes passantes relatives de 5% et 10% sont validés en mesures à 140 GHz et 280 GHz

    Effect of wafer-level silicon cap packaging on BiCMOS embedded RF-MEMS switch performance

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    In this paper, the effect of silicon (Si) cap packaging on the BiCMOS embedded RF-MEMS switch performance is studied. The RF-MEMS switches are designed and fabricated in a 0.25Όm SiGe BiCMOS technology for K-band (18 - 27 GHz) applications. The packaging is done based on a wafer-to-wafer bonding technique and the RF-MEMS switches are electrically characterized before and after the Si cap packaging. The experimental data shows the effect of the wafer-level Si cap package on the C-V and S-parameter measurements. The performed 3D FEM simulations prove that the low resistive Si cap, specifically 1Ω·cm, results in a significant RF performance degradation of the RF-MEMS switch in terms of insertion loss

    Full-wave RF modeling of a fan-out wafer-level packaging technology based on Al-Al wafer bonding

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    The transmission loss of a test structure, composed of a series of 18 CPW-based interconnections in between a High-Resistive Silicon (HRSi) interposer and a SiGe BiCMOS, produced by using the Al-Al bonding technology for FOWLP is discussed this paper. Its effectiveness as an alternative for mm-wave packaging platforms is proven by an overall S21 below 8 dB (< 0.2 dB/transition). Together with the experimental outcomes, the rigorous full-wave modeling of the configuration under investigation is also presented. Particular emphasis is placed on the chosen approach for addressing the criticalities that arise when it comes to simulate structures presenting different scales in their geometry. The validity of the model has been tested against the measured S-parameters, and a good accordance between the latter and the simulated results has been found, which makes the developed numerical platform a reliable tool for further optimization of the next generation of Al-Al FOWLP technology-based devices

    Modeling and optimization of BiCMOS embedded through-silicon vias for RF-grounding

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    In this paper we demonstrate the modeling and optimization of BiCMOS embedded high aspect ratio through-silicon vias (TSV) for RF-grounding applications. The inductance and the resistance of the TSV are analyzed with respect to TSV design parameters and process effects such as sidewall-tilting and void formation. RF measurement results with extracted inductance and resistance of 24 pH and 86 m for a single TSV are in very good agreement with the simulation results. Based on the simulated and measured results, RLC-lumped-element models are developed considering the aforementioned process characteristics to provide realistic models for Process-Design-Kit (PDK) implementation
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