29,547 research outputs found

    Nonlinear ER effects in an ac applied field

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    The electric field used in most electrorheological (ER) experiments is usually quite high, and nonlinear ER effects have been theoretically predicted and experimentally measured recently. A direct method of measuring the nonlinear ER effects is to examine the frequency dependence of the same effects. For a sinusoidal applied field, we calculate the ac response which generally includes higher harmonics. In is work, we develop a multiple image formula, and calculate the total dipole moments of a pair of dielectric spheres, embedded in a nonlinear host. The higher harmonics due to the nonlinearity are calculated systematically.Comment: Presented at Conference on Computational Physics (CCP2000), held at Gold Coast, Australia from 3-8, December 200

    The Financial Deepening-Productivity Nexus in China: 1987-2001

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    The financial intermediation-growth nexus is a widely studied topic in the literature of development economics. Deepening financial intermediation may promote economic growth by mobilizing more investments, and lifting returns to financial resources, which raises productivity. Relying on provincial panel data from China, this paper attempts to examine if regional productivity growth is accounted for by the deepening process of financial development. Towards this end, an appropriate measurement of financial depth is constructed and then included as a determinant of productivity growth. It finds that a significant and positive nexus exists between financial deepening and productivity growth. Given the divergent pattern of financial deepening between coastal and inland provinces, this finding also helps explain the rising regional disparity in China.growth, financial development, productivity, China

    Slopes for higher rank Artin-Schreier-Witt Towers

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    We fix a monic polynomial fˉ(x)Fq[x]\bar f(x) \in \mathbb{F}_q[x] over a finite field of characteristic pp, and consider the Zp\mathbb{Z}_{p^{\ell}}-Artin-Schreier-Witt tower defined by fˉ(x)\bar f(x); this is a tower of curves CmCm1C0=A1\cdots \to C_m \to C_{m-1} \to \cdots \to C_0 =\mathbb{A}^1, whose Galois group is canonically isomorphic to Zp\mathbb{Z}_{p^\ell}, the degree \ell unramified extension of Zp\mathbb{Z}_p, which is abstractly isomorphic to (Zp)(\mathbb{Z}_p)^\ell as a topological group. We study the Newton slopes of zeta functions of this tower of curves. This reduces to the study of the Newton slopes of L-functions associated to characters of the Galois group of this tower. We prove that, when the conductor of the character is large enough, the Newton slopes of the L-function asymptotically form a finite union of arithmetic progressions. As a corollary, we prove the spectral halo property of the spectral variety associated to the Zp\mathbb{Z}_{p^{\ell}}-Artin-Schreier-Witt tower. This extends the main result in [DWX] from rank one case =1\ell=1 to the higher rank case 1\ell\geq 1.Comment: 20 page

    Design of a 2.4 GHz High-Performance Up-Conversion Mixer with Current Mirror Topology

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    In this paper, a low voltage low power up-conversion mixer, designed in a Chartered 0.18 μm RFCMOS technology, is proposed to realize the transmitter front-end in the frequency band of 2.4 GHz. The up-conversion mixer uses the current mirror topology and current-bleeding technique in both the driver and switching stages with a simple degeneration resistor. The proposed mixer converts an input of 100 MHz intermediate frequency (IF) signal to an output of 2.4 GHz radio frequency (RF) signal, with a local oscillator (LO) power of 2 dBm at 2.3 GHz. A comparison with conventional CMOS up-conversion mixer shows that this mixer has advantages of low voltage, low power consumption and high-performance. The post-layout simulation results demonstrate that at 2.4 GHz, the circuit has a conversion gain of 7.1 dB, an input-referred third-order intercept point (IIP3) of 7.3 dBm and a noise figure of 11.9 dB, while drawing only 3.8 mA for the mixer core under a supply voltage of 1.2 V. The chip area including testing pads is only 0.62×0.65 mm2
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