Baby Skyrme models without a potential term

We develop a one-parameter family of static baby Skyrme models that do not require a potential term to admit topological solitons. This is a novel property as the standard baby Skyrme model must contain a potential term in order to have stable soliton solutions, though the Skyrme model does not require this. Our new models satisfy an energy bound that is linear in terms of the topological charge and can be saturated in an extreme limit. They also satisfy a virial theorem that is shared by the Skyrme model. We calculate the solitons of our new models numerically and observe that their form depends significantly on the choice of parameter. In one extreme, we find compactons while at the other there is a scale invariant model in which solitons can be obtained exactly as solutions to a Bogomolny equation. We provide an initial investigation into these solitons and compare them with the baby Skyrmions of other models

TTCPR: a PMC receiver for TTC

Abstract The TTCPR receiver is a mezzanine card intended for use in distributing TTC information to Data Acquisition and Trigger Crates in the ATLAS Prototype Integration activities. An original prototype run of these ~cards was built for testbeam and integration studies, implemented in both the PMC and PCI form factors, using the TTCrx chips from the previous manufacture. When the new TTCrx chips became available, the TTCPR was redesigned to take advantage of the availability and enhanced features of the new TTCRX(1), and a run of 20 PMC cards was manufactured, and has since been used in integration studies and the testbeam. The TTCPR uses the AMCC 5933(2) to manage the PCI port, an Altera 10K30A(3) to provide all the logic so that the functionality may be easily altered, and provides a 4K deep FIFO to retain TTC data for subsequent DMA through the PCI port. In addition to DMA's which are mastered by the Add On logic, communication through PCI is accomplished via mailboxes, interrupts, and the pass-through feature of the 5933. An interface to the I2C bus of the TTCRX is provided so that internal registers may be accessed, and the card supports reinitialization of the TTCRX from PCI. Software has been developed to support operation of the TTCPR under both LynxOS and Linux. I. History of the TTCPR The TTCPR was developed in response to a need for TTC(4) information in the Data Acquisition from TileCal Modules in the ATLAS Test Beam. Specifically, it was desired to have EventID, Bunch Counter, and Trigger Type available from TTC in the data records. It was useful to have the TTC information available to processors in the Data Acquisition crates through PCI ports, and to have the data transferred to the processor's address space via an externally mastered DMA. Accordingly, the TTCPR was designed as a mezzanine card in the PMC form factor. The original cards utilized the older nonradhard version of the TTCRX, because the new radhard version was not available at that time. When it became clear that the new TTCRX would be available soon and also that it would not be possible to obtain any more of the older TTCRX chips, the TTCPR was redesigned, and enhancements were added to take advantage of the features of the new TTCRX. This new TTCPR was produced and has been used successfully in data acquisition at the ATLAS Test Beam. The card has also been implemented in the PCI form factor. The TTCPR in the PMC version is shown in II. Architecture of the TTCPR A block diagram of the TTCPR is shown i

A Prototype ROI Builder for the Second Level Trigger of ATLAS Implemented in FPGAs

The design and implementation of a Region of Interest (ROI) Builder connecting the ATLAS Level 1 Trigger to the Level 2 Trigger Supervisor is described. A highly parallel design implemented in high large, high-speed FPGA's is described and results of tests are presented

ATLAS TDAQ RoI Builder and the Level 2 Supervisor system

The ATLAS High Level Trigger (HLT) uses information from the hardware based Level 1 Trigger system to guide the retrieval of information from the readout system. The Level 1 Trigger elements (jet, electromagnetic, muon candidate, etc.) determine Regions of Interest (RoIs) that seed further trigger decisions. This paper describes the device - the RoI Builder (RoIB) - that collects these data from the Level 1 Trigger and the Level 2 Supervisors (L2SV) Farm that makes these data available to the HLT. The status of the system design and the results of the tests and integration into ATLAS TDAQ system are presented

Development of a custom monolithic device for data acquisition from a scintillating calorimeter at the superconducting super collider

A clock-driven continuous sequential write/random read data acquisition architecture for a scintillating calorimeter at the SSC is presented. Simplicity of design and operation as well as potentially dead time-less operation are the motivations of this effort. The architecture minimizes the number of fast control signals, thereby reducing pickup from digital control lines by sensitive analog circuits in the front-end device. This architecture also reduces the logic necessary on the front-end device improving reliability and easing design and operation. Operation and design of the front-end device are discussed. 3 refs., 7 figs

Soudan 2 data acquisition and trigger electronics

The 1.1 kton Soudan 2 calorimetric drift-chamber detector is read out by 16K anode wires and 32K cathode strips. Preamps from each wire or strip are bussed together in groups of 8 to reduce the number of ADC channels. The resulting 6144 channels of ionization signal are flash-digitized every 200 ns and stored in RAM. The raw data hit patterns are continually compared with programmable trigger multiplicity and adjacency conditions. The data acquisition process is managed in a system of 24 parallel crates each containing an Intel 80C86 microprocessor, which supervises a pipe-lined data compactor, and allows transfer of the compacted data via CAMAC to the host computer. The 80C86's also manage the local trigger conditions and can perform some parallel processing of the data. Due to the scale of the system and multiplicity of identical channels, semi-custom gate array chips are used for much of the logic, utilizing 2.5 micron CMOS technology

The ATLAS High Level Trigger Region of Interest Builder

This article describes the design, testing and production of the ATLAS Region of Interest Builder (RoIB). This device acts as an interface between the Level 1 trigger and the high level trigger (HLT) farm for the ATLAS LHC detector. It distributes all of the level 1 data for a subset of events to a small number of (16 or less) individual commodity processors. These processors in turn provide this information to the HLT. This allows the HLT to use the level 1 information to narrow data requests to areas of the detector where level 1 has identified interesting objects.Comment: 13 pages, 7 figure

Radiative decays of decuplet hyperons

We calculate the radiative decay widths of decuplet hyperons in a chiral constituent quark model including electromagnetic exchange currents between quarks. Exchange currents contribute significantly to the E2 transition amplitude, while they largely cancel for the M1 transition amplitude. Strangeness suppression of the radiative hyperon decays is found to be weakened by exchange currents. Differences and similarities between our results and other recent model predictions are discussed.Comment: 11 pages, 1 eps figure, revtex, accepted for publication in Phys. Rev.